Patents by Inventor Vivek Swaminathan Sridharan
Vivek Swaminathan Sridharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11855024Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.Type: GrantFiled: August 31, 2021Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Qiao Chen, Vivek Swaminathan Sridharan, Christopher Daniel Manack, Patrick Francis Thompson, Jonathan Andrew Montoya, Salvatore Frank Pavone
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Patent number: 11854922Abstract: A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.Type: GrantFiled: June 21, 2021Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Vivek Swaminathan Sridharan, Christopher Daniel Manack, Joseph Liu
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Publication number: 20230317673Abstract: A described example includes: a reconstituted semiconductor device flip chip mounted on a device side surface of a package substrate, the package substrate having terminals for connecting the package substrate to a circuit board, the reconstituted semiconductor device further including: a semiconductor die mounted in a dielectric layer and having bond pads spaced from one another by at least a first pitch distance that is less than 100 microns; a redistribution layer formed over the bond pads having conductors in passivation layers; solder bumps on the redistribution layer coupled to the bond pads of the semiconductor die, the solder bumps spaced from one another by at least a second pitch distance that is greater than the first pitch distance; and solder joints formed between the package substrate and the solder bumps, the solder joints coupling the package substrate to the semiconductor die in the reconstituted semiconductor device.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Yiqi Tang, Vivek Swaminathan Sridharan, Rajen Manicon Murugan, Patrick Francis Thompson
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Publication number: 20230065075Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Qiao CHEN, Vivek Swaminathan SRIDHARAN, Christopher Daniel MANACK, Patrick Francis THOMPSON, Jonathan Andrew MONTOYA, Salvatore Frank PAVONE
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Publication number: 20220406673Abstract: A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.Type: ApplicationFiled: June 21, 2021Publication date: December 22, 2022Inventors: Vivek Swaminathan Sridharan, Christopher Daniel Manack, Joseph Liu
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Publication number: 20220384375Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Vivek Swaminathan Sridharan, Christopher Daniel Manack, Nazila Dadvand, Salvatore Frank Pavone, Patrick Francis Thompson
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Publication number: 20220328438Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Vivek Swaminathan SRIDHARAN, Christopher Daniel MANACK, Joseph LIU
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Publication number: 20220285293Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Vivek Swaminathan Sridharan, Yiqi Tang, Christopher Daniel Manack, Rajen Manicon Murugan, Liang Wan, Hiep Xuan Nguyen
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Patent number: 11410947Abstract: A package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. The package is a wafer chip scale package (WCSP). The package further includes a solder ball attached to the redistribution layer.Type: GrantFiled: December 19, 2019Date of Patent: August 9, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vivek Swaminathan Sridharan, Christopher Daniel Manack, Nazila Dadvand, Salvatore Frank Pavone, Patrick Francis Thompson
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Patent number: 11380637Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.Type: GrantFiled: November 17, 2020Date of Patent: July 5, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vivek Swaminathan Sridharan, Christopher Daniel Manack, Joseph Liu
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Patent number: 11362047Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.Type: GrantFiled: April 16, 2020Date of Patent: June 14, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vivek Swaminathan Sridharan, Yiqi Tang, Christopher Daniel Manack, Rajen Manicon Murugan, Liang Wan, Hiep Xuan Nguyen
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Publication number: 20210384150Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.Type: ApplicationFiled: November 17, 2020Publication date: December 9, 2021Inventors: Vivek Swaminathan SRIDHARAN, Christopher Daniel MANACK, Joseph LIU
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Publication number: 20210327829Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.Type: ApplicationFiled: April 16, 2020Publication date: October 21, 2021Inventors: Vivek Swaminathan Sridharan, Yiqi Tang, Christopher Daniel Manack, Rajen Manicon Murugan, Liang Wan, Hiep Xuan Nguyen
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Publication number: 20210210462Abstract: A semiconductor device includes a semiconductor surface having circuitry with metal interconnect layers over the semiconductor surface including a selected metal interconnect layer providing an interconnect trace having a first and second end. A top dielectric layer is on the top metal interconnect layer. A redistribution layer (RDL) is on the top dielectric layer. A corrosion interruption structure (CIS) including the interconnect trace bridges an interrupting gap in a trace of the RDL.Type: ApplicationFiled: January 6, 2020Publication date: July 8, 2021Inventors: Vivek Swaminathan Sridharan, Enis Tuncer, Christopher Daniel Manack, Patrick Francis Thompson
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Publication number: 20210193600Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Inventors: Vivek Swaminathan SRIDHARAN, Christopher Daniel MANACK, Nazila DADVAND, Salvatore Frank PAVONE, Patrick Francis THOMPSON
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Patent number: 10804233Abstract: Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.Type: GrantFiled: November 2, 2011Date of Patent: October 13, 2020Assignee: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Viren Khandekar, Karthik Thambidurai, Vivek Swaminathan Sridharan