Abstract: A method for scheduling operations utilized by an optimizing compiler to reduce register pressure on a target hardware platform assigns register economy priority (REP) values to each operation in a basic block. For each time slot, operations are scheduled in order of their lowest REP values.

Abstract: A method and apparatus for generating an optimized intermediate representation of source code for a computer program are described. An initial intermediate representation is extracted from the source code by organizing it as a plurality of basic blocks that each contain at least one program instruction ordered according to respective estimated profit values. A goal function that measures the degree of optimization of the program is calculated in accordance with its intermediate representation. The effect on the goal function of modifying the intermediate representation by moving an instruction from one of the basic blocks to each of its predecessors is tested iteratively and adopting the modified intermediate representation if it causes a reduction in the goal function.

Abstract: A method, implemented in a compiler, of balancing the workload between blocks in a control flow to reduce the overall execution time of control block includes steps for identifying “hard” blocks the consume excess resources, selecting hard block to unload, and unloading critical operations from a hard block to a control flow predecessor.

Abstract: A method and apparatus for optimizing scheduling of a block of program instructions to remove a condition resolving instruction from the critical path where the resolution of a condition controls the selection between input results, generated by predecessor operations, by a merge operation which passes the selected result to a successor operation. In a preferred embodiment, the successor operation is “unzipped” by duplicating the successor operations, providing predecessor results directly to the, duplicated successor operations, and scheduling the duplicated successor operations prior to the merge.

Abstract: A method and computer apparatus are presented for providing a secure data architecture for computer memory of a processor. The apparatus comprises a memory unit and a processing unit. Data are stored in the memory unit and manipulated by the processing unit, which is programmed to implement the data architecture. Tagged single data words are formed by concatenating a tag to each of the single data words. Each of the tags takes a value that corresponds to the data type of the single data word to which it is concatenated. A data multiword is creating by concatenating tagged single data words having the same data type. The data multiword is stored within a location in the computer memory, the location selected to ensure alignment of the data multiword in accordance with its length. An effective tag value is constructed for the data multiword by concatenating all of its single word tags.

Abstract: A compiler optimization method for optimizing a scheduled block of instructions inserts a conditional branch instruction in place of a merge instruction to select between alternative paths when a condition is resolved.

Abstract: Compiler optimization methods and systems for preventing delays associated with a speculative load operation on a data when the data is not in the data cache of a processor. A compiler optimizer analyzes various criteria to determine whether a cache miss savings transformation is useful. Depending on the results of the analysis, the load operation and/or the successor operations to the load operation are transferred into a predicated mode of operation to enhance overall system efficiency and execution speed.

Abstract: A method, implemented by a compiler, for removing a store-load dependency from a critical path utilizes a compare address operation to determine at run time whether dependency actual exists. The operand to be stored is held in a temporary register and provided directly to the operations, using load operation result, in dependence on the value of the compare address operation result, so that the dependency is removed.

Abstract: A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.

Abstract: A method for scheduling a plurality of operations of one or more types of operations including a plurality of computing resources is provided. The method includes building a list of partial lists for the one or more types of operations where the partial lists include one or more operations. A current partial list of a type of operation is determined. A computing resource for an operation in the current partial list is then allocated. The method then determines if additional computing resources for the type of operation are available for the current partial list. If so, the method reiterates back to determining a current partial list. If additional computing resources are not available, the method performs the steps of excluding the current partial list from the list and if the list includes any other partial lists, reiterating back to determining a current partial list.

Abstract: Computer method of compiling a multi-way decision statement for VLIW processing is described. The method comprises: (a) generating profile data for a multi-way decision statement, such a s a switch statement; identifying at least one most probable alternative of the multi-way decision and a set of constants associated with the identified alternative using the profile data; determining a probable subset of the identified constants based on the profile data; constructing a conditional statement for the identified alternative using the probable subset of constants; and moving out the identified at least one alternative from the multi-way decision statement.

Abstract: A method, implemented by a compiler, for removing a store-load dependency from a critical path utilizes a compare address operation to determine at run time whether dependency actual exists. The operand to be stored is held in a temporary register and provided directly to the operations, using load operation result, in dependence on the value of the compare address operation result, so that the dependency is removed.

Abstract: A method for scheduling operations utilized by an optimizing compiler to reduce register pressure on a target hardware platform assigns register economy priority (REP) values to each operation in a basic block. For each time slot, operations are scheduled in order of their lowest REP values.

Abstract: A method, implemented in a compiler, of balancing the workload between blocks in a control flow to reduce the overall execution time of control block includes steps for identifying “hard” blocks the consume excess resources, selecting hard block to unload, and unloading critical operations from a hard block to a control flow predecessor.

Abstract: A method and system for use with VLIW processing architectures for avoiding redundant speculative computations in the compilation of the innermost loops. The method includes identifying a plurality of compiled flow paths, where each of the paths includes a plurality of conditions associated with the loop that permits transformation of the loop for more optimum execution. It is then determined whether the loop has an inductive variable and a conditional statement that depends on the inductive variable. It is also determined whether the loop set up values of the inductive variables to subsets, and at least one of which the conditional statement is a loop invariant. Finally, if conditions in the determination steps satisfy the conditions of one of the paths, the loop is transformed into two consecutive loops executable with a reduced set of values of the inductive variable.

Abstract: An intermediate result signal arising from a manipulation of data signals is checked and reduced without using conditional branches, thereby improving instruction processing. Data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. A processor operating under program control with the program has the following operations. The program determines whether the intermediate result signal is in a positive overflow state or a negative overflow state. A first mask signal is set to have 8 lower bits in an OFF position when the intermediate result signal is inside the range of a signed 8 bit integer. Otherwise, the first mask signal is set to have 8 lower bits in an ON position.

Abstract: In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute value comprises the steps of: performing an arithmetic shift right of N-1 bit to form a bit mask; performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits. Further, an apparatus for parallel processing a signed value to form an absolute value comprises: means for performing an arithmetic shift right of N-1 bit to form a bit mask; means for performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and means for subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits.

Abstract: The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. In the preferred embodiment of the present invention, the data signals are represented as signed 16-bit binary values in a two's compliment format. An intermediate register is used to hold the intermediate signal which is greater than 16-bits in width to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control. The program determines whether the intermediate signal is in a positive or negative overflow state.

Abstract: A method for handling an overflow condition in a processor is disclosed. A first plurality of signal data is packed into a first memory location so as to form a first word. A second plurality of signal data is packed into a second memory location so as to form a second word. A bitwise operation is then performed between the first word and the second word to produce a result. The result of the operation is then stored in a k bit memory location so as to form a third word. The third word is then shifted left (k-9) bits. A bit mask is then obtained by arithmetic shifting the third word right (k-1) bits. A logical OR operation is then performed between the bit mask and the result.

Abstract: The present invention is directed to checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor. In the preferred embodiment of the present invention, the data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control with the program having the following operations. The program determines whether the intermediate result signal is in a positive overflow state or a negative overflow state. The program sets a first mask signal to have 8 lower bits in an OFF position when the intermediate result signal is inside the range of a signed 8 bit integer.