Patents by Inventor Vladislav Vashchenko

Vladislav Vashchenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High holding voltage LVTSCR-like structure
    Patent number: 7943958
    Abstract: In an ESD protection device making use of a LVTSCR structure, the holding voltage is increased by forming diodes in the p-well of the LVTSCR structure. This provides an alternative current path at high currents and provides a defined voltage drop thereby increasing the holding voltage.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: May 17, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Lateral resurf NPN with high holding voltage for ESD applications
    Patent number: 7935605
    Abstract: In an ESD protection circuit an NPN BJT snapback device is provided with high breakdown voltage by including a RESURF region or by forming a PIN diode in the BJT. Holding voltage is increased by forming a sub-collector sinker region with the desired configuration.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: May 3, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Compact dual direction BJT clamps
    Patent number: 7932582
    Abstract: In a dual direction BJT clamp, multiple emitter and base fingers are alternatingly connected to ground and pad and share a common sub-collector.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: April 26, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Method and structure for avoiding hot carrier degradation and soft leakage damage to ESD protection circuit
    Patent number: 7929262
    Abstract: In a ESD protection device, hot carrier degradation and soft leakage are reduced by introducing a dynamic driver that includes a RC circuit for keeping the triggering circuit of the ESD device in an on-state for a certain period of time. This allows the current through the ESD protection device to be reduced during the RC delay time.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: April 19, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter Hopper, Ann Concannon
  • Snapback capable NLDMOS, DMOS and extended voltage NMOS devices
    Patent number: 7915678
    Abstract: In an NLDMOS, DMOS and NMOS device, the ability is provided for withstanding snapback conditions by providing one or more p+ emitter regions interdigitated between drain regions having drain contacts and electrically connecting the drain contacts to contacts of the emitter regions.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: March 29, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • High voltage ESD LDMOS-SCR with gate reference voltage
    Patent number: 7910950
    Abstract: In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: March 22, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Low side zener reference voltage extended drain SCR clamps
    Patent number: 7910951
    Abstract: In a CMOS implemented free or parasitic pnp transistor, triggering is controlled by introducing a low side zener reference voltage.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: March 22, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Fuse-type memory cells based on irreversible snapback device
    Patent number: 7911869
    Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: March 22, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski
  • METHOD OF SWITCHING A MAGNETIC MEMS SWITCH
    Publication number: 20100295638
    Abstract: A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.
    Type: Application
    Filed: August 9, 2010
    Publication date: November 25, 2010
    Applicant: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Trevor Niblock, Peter Johnson, Vladislav Vashchenko
  • Magnetic MEMS switching regulator
    Patent number: 7839242
    Abstract: A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: November 23, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Trevor Niblock, Peter Johnson, Vladislav Vashchenko
  • ESD protection device with controllable triggering characteristics using driver circuit related to power supply
    Patent number: 7800127
    Abstract: In an ESD device for fast switching applications based on a BSCR or NLDMOS-SCR, an anode junction control electrode is provided by not connecting the anode electrode to the collector of the BSCR or to the drain of the NLDMOS-SCR, and a cathode junction control electrode is provided by forming an additional n+ region in the BSCR or an additional p+ region in the p-well of the NLDMOS-SCR. The triggering voltage of the ESD device is adjusted after a time delay by controlling one or both of the control electrodes using an RC-timer-driver circuit.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: September 21, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Alexander Burinskiy, Peter J. Hopper, Vladimir Kuznetsov
  • On chip battery
    Patent number: 7794510
    Abstract: In an on chip battery and method of making an on-chip battery, the electrodes are formed from metal layers deposited as part of the chip fabrication process. An electrolyte is preferably introduced between the electrodes at time of packaging of the chip.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: September 14, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Robert Drury, Vladislav Vashchenko
  • Current balancing in NPN BJT and BSCR snapback devices
    Patent number: 7795047
    Abstract: In a method and structure for current balancing the emitter current in a multi-finger n-emitter of a BJT or BSCR, back-end or polysilicon resistors are applied between the emitter fingers and the power rail, with the resistors chosen to be larger the closer the emitter fingers are to the collector.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: September 14, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • ESD high frequency diodes
    Patent number: 7795102
    Abstract: In a SiGe BJT process, a diode is formed by defining a p-n junction between the BJT collector and BJT internal base, blocking the external gate regions of the BJT and doping the emitter poly of the BJT with the same dopant type as the internal base thereby using the emitter contact to define the contact to the internal base. Electrical contact to the collector is established through a sub-collector or by means of a second emitter poly and internal base both doped with the same dopant type as the collector.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: September 14, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Vladimir Kuznetsov, Peter J. Hopper
  • Method of forming a SiGe DIAC ESD protection structure
    Patent number: 7754540
    Abstract: A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: July 13, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Method of forming a silicon-based light-emitting structure
    Patent number: 7754505
    Abstract: A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: July 13, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, William French, Vladislav Vashchenko
  • ESD clamps and NMOS arrays with increased electrical overstress robustness
    Patent number: 7718480
    Abstract: In an NMOS active clamp device and an NMOS active clamp array with multiple source and drain contacts, the robustness against ESD events is increased by reducing channel resistance through the inclusion of one or more p+ regions formed at least partially in the source and electrically connected to the one or more source contacts.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: May 18, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Marcel ter Book, Peter J. Hopper
  • Method of controlling the breakdown voltage of BSCRs and BJT clamps
    Patent number: 7714355
    Abstract: In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: May 11, 2010
    Assignee: National Semiconductor Corp
    Inventors: Vladislav Vashchenko, Alexei Sadovnikov, Peter J. Hopper, Andy Strachan
  • Split-gate ESD diodes with elevated voltage tolerance
    Publication number: 20100102391
    Abstract: In a gated diode ESD protection structure, the gate is split into two parts to divide the total reverse voltage between two gate regions.
    Type: Application
    Filed: October 27, 2008
    Publication date: April 29, 2010
    Inventors: Vladislav Vashchenko, Konstantin G. Korablev
  • Gated diode with increased voltage tolerance
    Publication number: 20100102390
    Abstract: In a gated diode ESD protection structure, the gate is biased to a voltage higher than ground and gate size is reduced while ensuring adequate spacing between p+ and n+ regions of the diode by blocking at least one of n-lightly doped region and p-lightly doped region.
    Type: Application
    Filed: October 27, 2008
    Publication date: April 29, 2010
    Inventors: Vladislav Vashchenko, Konstantin G. Korablev