Abstract: A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The microprocessor unit comprises a register that contains particular bit fields for defining selectable power modes. The particular bit fields in the register define pointers to a power mode defining register. Each pointer selects a corresponding bit field in the power mode defining register. The bits in the bit fields of the power mode defining register either directly control a power mode of at least one functional or peripheral blocks of the unit; or they are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional or peripheral blocks of the unit.

Abstract: An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor which is then disconnected from the integrated circuit power supply. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged and disconnected from the power supply. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.

Abstract: A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The microprocessor unit comprises a register that contains particular bit fields for defining selectable power modes. The particular bit fields in the register define pointers to a power mode defining register. Each pointer selects a corresponding bit field in the power mode defining register. The bits in the bit fields of the power mode defining register either directly control a power mode of at least one functional or peripheral blocks of the unit; or they are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional or peripheral blocks of the unit.

Abstract: An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state.

Abstract: An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.

Abstract: An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state.

Abstract: The invention relates to an electronic device, a debug unit and to a method for estimating a power consumption of an application that is executable on an electronic device having a plurality of modules. A status of at least one routine of the application and a status of at least one module of the electronic device is determined. Further a power consumption of the at least one module is estimated by allocating a predetermined power consumption value to the detected status of the respective module. The determined status of the routine may be assigned to the determined status of the at least one module and to the estimated power consumption of the module so as to provide an estimated power consumption of the application.

Abstract: An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin (TMS), a test clock pin (TCK), and a test access port (TAP) controller having a data register (DR) shift state and an instruction register shift (IR) state. The electronic device operates in a scan event mode automatically mapped an incoming event to the TDO pin.

Abstract: An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin (TMS), a test clock pin (TCK), and a test access port (TAP) controller having a data register (DR) shift state and an instruction register shift (IR) state. The electronic device operates in a scan event mode automatically mapped an incoming event to the TDO pin.

Abstract: The present invention relates to an electronic device for analog-to-digital conversion including a sigma-delta modulator (SD), a digital filter (FIL) for digital post processing of the output signal of the sigma-delta modulator (SD), a multiplexer (MUX) for switching the input (INSD) of the sigma-delta modulator between a first input signal (IN1) and a second input signal (IN2), a memory (MEM) adapted to hold the register content of the digital filter relating to the first input signal while the second input signal (IN2) is processed in the digital filter, and a controller (CNTL) to retrieve the register contents from the memory (MEM) when processing of the first input signal (IN1) in the digital filter is resumed.

Abstract: An electronic energy meter includes a first sigma delta modulator having an electrically isolated digital data output. A power supply stage coupled to a first electrical line provides a supply voltage to the first sigma delta modulator. A shunt device is also coupled to the first electrical line. The first sigma delta modulator is coupled via an input to the shunt device for measuring a current through the first electrical line. The electrically isolated digital output is isolated by a capacitive isolation barrier.

Abstract: A polyphase electric energy meter is provided that includes a microcontroller with a front end that converts analog current input signals and analog voltage input signals to digital current and voltage samples for processing by the microcontroller. The front end includes separate input channels, each for one of the current input signals with a sigma-delta modulator followed by a decimation filter. The front end further includes a common input channel for all voltage input signals with a multiplexer, an analog-to-digital converter and a de-multiplexer. The separate input channels and the common input channel provide the digital current and voltage samples for processing by the microcontroller.

Abstract: A polyphase electric energy meter comprises a microcontroller with a front end that converts analog current input signals and analog voltage input signals to digital current and voltage samples for processing by the microcontroller. The front end includes separate input channels, each for one of the current input signals with a sigma-delta modulator followed by a decimation filter. The front end further includes a common input channel for all voltage input signals with a multiplexer, an analog-to-digital converter and a de-multiplexer. The separate input channels and the common input channel provide the digital current and voltage samples for processing by the microcontroller.

Abstract: A poly-phase electric energy meter comprises a front-end that converts analog current input signals and analog voltage input signals to digital current and voltage samples and a micro-controller for computing power consumed. The front end includes first and second input channels. Each input channel has a multiplexer, an analog-digital converter, a de-multiplexer and a set of data registers. The first input channel receives current input and the second input channel receives voltage inputs. A multiplexer control causes the first and second channels to sequentially sample the current and voltage for one phase at a time and store digital data in corresponding data registers. The micro-controller computes energy consumed from the simultaneous current and voltage samples.

Abstract: An electronic energy meter includes a first sigma delta modulator having an electrically isolated digital data output. A power supply stage coupled to a first electrical line provides a supply voltage to the first sigma delta modulator. A shunt device is also coupled to the first electrical line. The first sigma delta modulator is coupled via an input to the shunt device for measuring a current through the first electrical line. The electrically isolated digital output is isolated by a capacitive isolation barrier.

Abstract: The present invention relates to an electronic device for analog-to-digital conversion including a sigma-delta modulator (SD), a digital filter (FIL) for digital post processing of the output signal of the sigma-delta modulator (SD), a multiplexer (MUX) for switching the input (INSD) of the sigma-delta modulator between a first input signal (IN1) and a second input signal (IN2), a memory (MEM) adapted to hold the register content of the digital filter relating to the first input signal while the second input signal (IN2) is processed in the digital filter, and a controller (CNTL) to retrieve the register contents from the memory (MEM) when processing of the first input signal (IN1) in the digital filter is resumed.

Abstract: A polyphase electric energy meter comprises a microcontroller with a front end that converts analog current input signals and analog voltage input signals to digital current and voltage samples for processing by the microcontroller. The front end includes separate input channels, each for one of the current input signals with a sigma-delta modulator followed by a decimation filter. The front end further includes a common input channel for all voltage input signals with a multiplexer, an analog-to-digital converter and a de-multiplexer. The separate input channels and the common input channel provide the digital current and voltage samples for processing by the microcontroller.

Abstract: A poly-phase electric energy meter comprises a front-end that converts analog current input signals and analog voltage input signals to digital current and voltage samples and a micro-controller for computing power consumed. The front end includes first and second input channels. Each input channel has a multiplexer, an analog-digital converter, a de-multiplexer and a set of data registers. The first input channel receives current input and the second input channel receives voltage inputs. A multiplexer control causes the first and second channels to sequentially sample the current and voltage for one phase at a time and store digital data in corresponding data registers. The micro-controller computes energy consumed from the simultaneous current and voltage samples.