Patents by Inventor Voon-Yew Thean

Voon-Yew Thean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7659156
    Abstract: A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: February 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Marc Rossow, Gregory S. Spencer, Tab A. Stephens, Dina H. Triyoso, Victor H. Vartanian
  • Publication number: 20100027355
    Abstract: A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top surface, an electrically conductive top gate electrode overlying the top gate dielectric, a bottom gate dielectric underlying the semiconductor body bottom surface, an electrically conductive bottom gate electrode underlying the bottom gate dielectric, and a charge trapping layer. The charge trapping layer includes a plurality of shallow charge traps, adjacent the top or bottom surface of the semiconductor body. The charge trapping layer may be of aluminum oxide, silicon nitride, or silicon nanoclusters. The charge trapping layer may located positioned between the bottom gate dielectric and the bottom surface of the semiconductor body.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 4, 2010
    Inventors: Thuy B. Dao, Voon-Yew Thean, Bruce E. White
  • Publication number: 20100013021
    Abstract: Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
    Type: Application
    Filed: July 21, 2008
    Publication date: January 21, 2010
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR INC., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xiangdong Chen, Jong Ho Lee, Weipeng Li, Dae-Gyu Park, Kenneth J. Stein, Voon-Yew Thean
  • Publication number: 20090291540
    Abstract: A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 26, 2009
    Inventors: Da Zhang, Srikanth B. Samavedam, Voon-Yew Thean, Xiangdong Chen
  • Publication number: 20090289280
    Abstract: A semiconductor process and apparatus includes forming <100> channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming a PMOS gate structure (36) overlying the channel region layer, and then depositing a neutral (53) or compressive (55) contact etch stop layer over the PMOS gate structure. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 26, 2009
    Inventors: Da Zhang, Srikanth B. Samavedam, Voon-Yew Thean, Xiangdong Chen
  • Publication number: 20090286387
    Abstract: A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (14) over a gate dielectric layer (12) and then selectively introducing nitrogen into the portions of the first conductive layer (14) in the PMOS device region (1), either by annealing (42) a nitrogen-containing diffusion layer (22) formed in the PMOS device region (1) or by performing an ammonia anneal process (82) while the NMOS device region (2) is masked. By introducing nitrogen into the first conductive layer (14), the work function is modulated toward PMOS band edge.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 19, 2009
    Inventors: David C. Gilmer, Srikanth B. Samavedam, James K. Schaeffer, Voon-Yew Thean
  • Patent number: 7615806
    Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: November 10, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Jian Chen, Bich-Yen Nguyen, Mariam G. Sadaka, Da Zhang
  • Patent number: 7585735
    Abstract: A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: September 8, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Yang Du, Bich-Yen Nguyen, Voon-Yew Thean
  • Patent number: 7575975
    Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 18, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Jian Chen, Bich-Yen Nguyen, Mariam G. Sadaka, Da Zhang
  • Patent number: 7556992
    Abstract: A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a <110> crystallographic orientation and a second semiconductor layer (405) having a <100> crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: July 7, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhonghai Shi, Voon-Yew Thean, Ted R. White
  • Patent number: 7521720
    Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: April 21, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Yang Du, Voon-Yew Thean
  • Patent number: 7494832
    Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Yang Du, Voon-Yew Thean
  • Patent number: 7468313
    Abstract: A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer. The wafer's active layer is biaxially strained and has first and second regions. The second region is amorphized to alter its strain component(s). The wafer is annealed to re-crystallize the amorphous semiconductor. First and second types of transistors are fabricated in the first region and the second region respectively. Third and possibly fourth regions of the active layer may be processed to alter their strain characteristics. A sacrificial strain structure may be formed overlying the third region. The strain structure may be a compressive. When annealing the wafer with the strain structure in place, its strain characteristics may be mirrored in the third active layer region. The fourth active layer region may be amorphized in stripes that run parallel to a width direction of the transistor strain to produce uniaxial stress in the width direction.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: December 23, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Victor H. Vartanian, Brian A. Winstead
  • Publication number: 20080299724
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Darren V. Goedeke, Voon-Yew Thean, Stefan Zollner
  • Publication number: 20080299717
    Abstract: A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Inventors: Brian A. Winstead, Konstantin V. Loiko, Voon-Yew Thean
  • Publication number: 20080258219
    Abstract: A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
    Type: Application
    Filed: April 18, 2007
    Publication date: October 23, 2008
    Inventors: Voon-Yew Thean, Marc Rossow, Gregory S. Spencer, Tab A. Stephens, Dina H. Triyoso, Victor H. Vartanian
  • Publication number: 20080237635
    Abstract: A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly over the oxide layer. The semiconductor device further includes a second semiconductor layer (26) having a second lattice constant formed directly over the first semiconductor layer, wherein the second lattice constant is different from the first lattice constant.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Voon-Yew Thean, Bich-Yen Nguyen
  • Patent number: 7419866
    Abstract: A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: September 2, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mariam G. Sadaka, Bich-Yen Nguyen, Voon-Yew Thean
  • Publication number: 20080188067
    Abstract: A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Leo Mathew, Voon-Yew Thean, Vishal P. Trivedi
  • Publication number: 20080124858
    Abstract: A semiconductor fabrication process includes forming an NMOS gate electrode overlying a biaxially strained NMOS active region and forming a PMOS gate electrode overlying a biaxially strained PMOS active region. Amorphous silicon is created in a PMOS source/drain region to reduce PMOS channel direction tensile stress. A PMOS source/drain implant is performed in the amorphous PMOS source/drain. Creating amorphous silicon in the PMOS source/drain may include implanting an electrically neutral species (e.g., Ge, Ga, or Xe). The wafer then may be annealed and a second PMOS amorphizing implant performed. PMOS halo, source/drain extension, and deep source/drain implants may then be performed. Following the first amorphizing implant, a sacrificial compressive stressor may be formed over the PMOS region, the wafer annealed to recrystallize the amorphous PMOS region, and the compressive stressor removed.
    Type: Application
    Filed: August 7, 2006
    Publication date: May 29, 2008
    Inventors: Bich-Yen Nguyen, Voon-Yew Thean