Patents by Inventor Voon-Yew Thean

Voon-Yew Thean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7230264
    Abstract: A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the semiconductor substrate and adjacent the control electrode to form a channel within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: June 12, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Dina H. Triyoso, Bich-Yen Nguyen
  • Publication number: 20070126076
    Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.
    Type: Application
    Filed: August 17, 2006
    Publication date: June 7, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Yang Du, Voon-Yew Thean
  • Patent number: 7226820
    Abstract: A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: June 5, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Jing Liu, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White
  • Patent number: 7226833
    Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: June 5, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ted R. White, Alexander L. Barr, Bich-Yen Nguyen, Marius K. Orlowski, Mariam G. Sadaka, Voon-Yew Thean
  • Publication number: 20070108481
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Brian Goolsby, Linda McCormick, Bich-Yen Nguyen, Colita Parker, Mariam Sadaka, Victor Vartanian, Ted White, Melissa Zavala
  • Publication number: 20070099353
    Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Voon-Yew Thean, Jian Chen, Bich-Yen Nguyen, Mariam Sadaka, Da Zhang
  • Publication number: 20070099361
    Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Voon-Yew Thean, Jian Chen, Bich-Yen Nguyen, Mariam Sadaka, Da Zhang
  • Patent number: 7208424
    Abstract: A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: April 24, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tab A. Stephens, Brian J. Goolsby, Bich-Yen Nguyen, Voon-Yew Thean
  • Patent number: 7208357
    Abstract: A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: April 24, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mariam G. Sadaka, Alexander L. Barr, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White
  • Patent number: 7205210
    Abstract: A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the <100> direction and at a 45 degree angle to the <100> direction of the base silicon layer of the second silicon.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: April 17, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alexander L. Barr, Dejan Jovanovic, Bich-Yen Nguyen, Mariam G. Sadaka, Voon-Yew Thean, Ted R. White
  • Publication number: 20070026615
    Abstract: A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate (18) and channel (23) connected via source/drain extensions (22, 24) which form a fin. At small dimensions, ion implanting may cause irreparable crystal damage to any thin areas of silicon such as the fin area. To permit a high concentration/low resistance source/drain extension, a sacrificial doping layer (28, 30) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 1, 2007
    Inventors: Sinan Goktepeli, Voon-Yew Thean
  • Patent number: 7160769
    Abstract: P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the <100> direction. The wide channel width P channel transistors are preferably oriented in the <110> direction.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: January 9, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ted R. White, Alexander L. Barr, Dejan Jovanovic, Bich-Yen Nguyen, Mariam G. Sadaka, Voon-Yew Thean
  • Publication number: 20060228842
    Abstract: A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 12, 2006
    Inventors: Da Zhang, Jing Liu, Bich-Yen Nguyen, Voon-Yew Thean, Ted White
  • Publication number: 20060228872
    Abstract: A method of forming a semiconductor device includes forming a local strain-inducing structure of a first semiconductor material at a point location within a dielectric layer. The local strain-inducing structure has a prescribed geometry with a surface disposed above a surface of the dielectric layer. A second semiconductor material is formed over the dielectric layer and the local strain inducing structure, wherein formation of a first portion of the second material over the dielectric layer provides a poly crystalline structure of the second material and wherein formation of a second portion of the second material over the local strain-inducing structure provides a single crystalline structure of the second material subject to mechanical strain by the surface of the local strain-inducing structure. The single crystalline structure serves as a strained semiconductor layer of the semiconductor device.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 12, 2006
    Inventors: Bich-Yen Nguyen, Shawn Thomas, Lubomir Cergel, Mariam Sadaka, Voon-Yew Thean, Peter Wennekers, Ted White, Andreas Wild, Detlev Gruetzmacher, Oliver Schmidt
  • Publication number: 20060228851
    Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 12, 2006
    Inventors: Mariam Sadaka, Alexander Barr, Dejan Jovanovic, Bich-Yen Nguyen, Voon-Yew Thean, Shawn Thomas, Ted White
  • Publication number: 20060226492
    Abstract: A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. In addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 12, 2006
    Inventors: Bich-Yen Nguyen, Shawn Thomas, Lubomir Cergel, Mariam Sadaka, Voon-Yew Thean, Peter Wennekers, Ted White, Andreas Wild, Detlev Gruetzmacher, Oliver Schmidt
  • Publication number: 20060228863
    Abstract: A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.
    Type: Application
    Filed: March 29, 2005
    Publication date: October 12, 2006
    Inventors: Da Zhang, Bich-Yen Nguyen, Voon-Yew Thean, Yasuhito Shiho, Veer Dhandapani
  • Publication number: 20060220157
    Abstract: A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Sriram Kalpat, Voon-Yew Thean, Hsing Tseng, Olubunmi Adetutu
  • Patent number: 7112455
    Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: September 26, 2006
    Assignee: Freescale Semiconductor, INC
    Inventors: Leo Mathew, Yang Du, Voon-Yew Thean
  • Patent number: 7091071
    Abstract: A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: August 15, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Brian J. Goolsby, Bich-Yen Nguyen, Thien T. Nguyen, Tab A. Stephens