Patents by Inventor Wai Cheung Law

Wai Cheung Law has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Spin diode devices
    Patent number: 11751483
    Abstract: According to various embodiments, a spin diode device may include a magnetic tunnel junction stack. The magnetic tunnel junction stack may include a lower magnetic layer, a tunnel barrier layer over the lower magnetic layer, and an upper magnetic layer over the tunnel barrier layer. The lower magnetic layer may include a lower magnetic film. The tunnel barrier layer comprising an insulating material. The upper magnetic layer may include an upper magnetic film. Each of the lower magnetic film and the upper magnetic film may have perpendicular magnetic anisotropy.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 5, 2023
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wai Cheung Law, Grayson Dao Hwee Wong, Kazutaka Yamane, Chim Seng Seet, Wen Siang Lew
  • SPIN DIODE DEVICES
    Publication number: 20220209102
    Abstract: According to various embodiments, a spin diode device may include a magnetic tunnel junction stack. The magnetic tunnel junction stack may include a lower magnetic layer, a tunnel barrier layer over the lower magnetic layer, and an upper magnetic layer over the tunnel barrier layer. The lower magnetic layer may include a lower magnetic film. The tunnel barrier layer comprising an insulating material. The upper magnetic layer may include an upper magnetic film. Each of the lower magnetic film and the upper magnetic film may have perpendicular magnetic anisotropy.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Inventors: Wai Cheung LAW, Grayson Dao Hwee WONG, Kazutaka YAMANE, Chim Seng SEET, Wen Siang LEW
  • MAGNETIC TUNNEL JUNCTION DEVICES AND METHODS OF FORMING THEREOF
    Publication number: 20210159393
    Abstract: In a non-limiting embodiment, a semiconductor device may include a magnetic tunnel junction (MTJ) stack. The MTJ stack may include a reference layer comprising a magnetic layer, a first tunneling barrier layer arranged over the reference layer, a free layer comprising a magnetic layer arranged over the first tunneling barrier layer, and a capping layer arranged over the reference layer, the first tunneling barrier layer and the free layer. The capping layer may be a non-magnetic layer. According to various non-limiting embodiments, the capping layer may include a rare earth element. According to various non-limiting embodiments, the MTJ stack may further include a second tunneling barrier layer arranged between the free layer and the capping layer. The capping layer may contact the second tunneling barrier layer.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventors: Wai Cheung LAW, Ganesh KOLLIYIL RAJAN, Yuichi OTANI, Kazutaka YAMANE, Chim Seng SEET, Grayson Dao Hwee WONG
  • Integrated circuits with magnetic tunnel junctions and methods of producing the same
    Patent number: 10475495
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Chim Seng Seet, Kai Hung Alex See, Gerard Joseph Lim, Wen Siang Lew
  • Integrated circuits with magnetic tunnel junctions and methods of producing the same
    Patent number: 10468171
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Dimitri Houssameddine, Michael Nicolas Albert Tran, Chim Seng Seet, Kai Hung Alex See, Wen Siang Lew
  • INTEGRATED CIRCUITS WITH MAGNETIC TUNNEL JUNCTIONS AND METHODS OF PRODUCING THE SAME
    Publication number: 20190252600
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.
    Type: Application
    Filed: February 14, 2018
    Publication date: August 15, 2019
    Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Chim Seng Seet, Kai Hung Alex See, Gerard Joseph Lim, Wen Siang Lew