Patents by Inventor Wai Yew Lo

Wai Yew Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming a substrateless semiconductor package
    Patent number: 7160755
    Abstract: A method of forming a substrateless semiconductor package (10) includes forming a carrier (16) on a base plate (12) and attaching an integrated circuit (IC) die (32) to the carrier (16). The IC die (32) then is electrically connected to the carrier (16). A molding operation is performed to encapsulate the IC die (32), the electrical connections (36) and the carrier (16). Thereafter, the base plate (12) is removed.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: January 9, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Wai Yew Lo, Cheng Choi Yong, Kong Bee Tiu
  • Stacked die semiconductor device
    Patent number: 6885093
    Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: April 26, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Wai Yew Lo, Azhar Bin Aripin, Kong Bee Tiu
  • Stacked die semiconductor device
    Publication number: 20030160312
    Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).
    Type: Application
    Filed: February 28, 2002
    Publication date: August 28, 2003
    Inventors: Wai Yew Lo, Azhar Bin Aripin, Kong Bee Tiu
  • Stacked die semiconductor device
    Publication number: 20030160311
    Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface attached to the base carrier top side (108), and a top integrated circuit die (106 attached to a top surface of the bottom die (104). The top die (106) is attached to the bottom die (104) with a die attach material (118) having particles (120) blended therein is dispensed onto the top surface of the bottom die. The particles (120) blended into the die attach material (118) maintain a predetermined spacing between the bottom die and the top die so that wirebonds connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).
    Type: Application
    Filed: February 28, 2002
    Publication date: August 28, 2003
    Inventors: Aminuddin Ismail, Wai Yew Lo, Kim Heng Tan