Patents by Inventor Wakana KAI

Wakana KAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9449848
    Abstract: According to one embodiment, the manufacturing method for the semiconductor device according to the embodiment includes carrying out ion implantation to the semiconductor layer and forming an amorphous layer on the surface of the semiconductor layer, and a heat treatment process using microwave annealing at a temperature higher than or equal to 200° C. and lower than or equal to 700° C. and single crystallizes the amorphous layer.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: September 20, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaka Miyano, Wakana Kai, Tatsunori Isogai, Tomonori Aoyama
  • Patent number: 8883642
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a concave portion on a surface of a substrate to be processed. The method further includes forming a coating film on the substrate to embed the coating film in the concave portion. The method further includes performing a first heat treatment in an atmosphere including an oxidant which contains polar molecules. The method further includes performing a second heat treatment after the first heat treatment by irradiating the coating film with a microwave after or while exposing the coating film to a liquid or a gas containing polar molecules.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wakana Kai, Tomonori Aoyama
  • Publication number: 20140087547
    Abstract: According to one embodiment, the manufacturing method for the semiconductor device according to the embodiment includes carrying out ion implantation to the semiconductor layer and forming an amorphous layer on the surface of the semiconductor layer, and a heat treatment process using microwave annealing at a temperature higher than or equal to 200° C. and lower than or equal to 700° C. and single crystallizes the amorphous layer.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaka MIYANO, Wakana KAI, Tatsunori ISOGAI, Tomonori AOYAMA
  • Publication number: 20130280911
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a concave portion on a surface of a substrate to be processed. The method further includes forming a coating film on the substrate to embed the coating film in the concave portion. The method further includes performing a first heat treatment in an atmosphere including an oxidant which contains polar molecules. The method further includes performing a second heat treatment after the first heat treatment by irradiating the coating film with a microwave after or while exposing the coating film to a liquid or a gas containing polar molecules.
    Type: Application
    Filed: February 28, 2013
    Publication date: October 24, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Wakana KAI, Tomonori AOYAMA
  • Patent number: 8558354
    Abstract: According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Iwakaji, Jun Hirota, Moto Yabuki, Wakana Kai, Hirokazu Ishida, Ichiro Mizushima
  • Patent number: 8481989
    Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnect layer, a bit line interconnect layer and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction intersecting with the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar has a selector stacked film containing silicon, and a variable resistance film disposed on a side of the word lines or the bit lines. The selector stacked film has a different component-containing layer. The different component-containing layer is formed at one position in a region excluding ends on the sides of the word and bit lines, and contains a 14 group element having a larger atomic radius than an atomic radius of silicon.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: July 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wakana Kai, Hirokazu Ishida
  • Publication number: 20120091414
    Abstract: According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.
    Type: Application
    Filed: March 21, 2011
    Publication date: April 19, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoko IWAKAJI, Jun Hirota, Moto Yabuki, Wakana Kai, Hirokazu Ishida, Ichiro Mizushima
  • Publication number: 20110291063
    Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnect layer, a bit line interconnect layer and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction intersecting with the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar has a selector stacked film containing silicon, and a variable resistance film disposed on a side of the word lines or the bit lines. The selector stacked film has a different component-containing layer. The different component-containing layer is formed at one position in a region excluding ends on the sides of the word and bit lines, and contains a 14 group element having a larger atomic radius than an atomic radius of silicon.
    Type: Application
    Filed: April 26, 2011
    Publication date: December 1, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Wakana KAI, Hirokazu Ishida