Patents by Inventor Walid M. Hafez

Walid M. Hafez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200266278
    Abstract: A semiconductor device structure having a “T-shaped” gate structure is described. A narrower first portion supports high frequency processes (e.g., gigahertz wireless communications). A second portion of the gate structure has a second width greater than the first width. Lateral extensions (sometimes referred to as “field plates), thinner and wider than the second portion, extend from the second portion. This combination of a gate structure having a narrow first portion and a wider second portion improves the performance of the semiconductor device in applications that involve both high frequency and high power consumption.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Applicant: INTEL CORPORATION
    Inventors: Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Han Wui THEN, Paul B. FISCHER, Walid M. HAFEZ
  • Patent number: 10741640
    Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan
  • Publication number: 20200251471
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe
  • Publication number: 20200251470
    Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
    Type: Application
    Filed: April 13, 2020
    Publication date: August 6, 2020
    Inventors: Curtis TSAI, Chia-Hong JAN, Jeng-Ya David YEH, Joodong PARK, Walid M. HAFEZ
  • Publication number: 20200227407
    Abstract: Disclosed herein are IC structures, packages, and devices that include polysilicon resistors, monolithically integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a polysilicon resistor provided over a second portion of the III-N material. Because the III-N transistor and the polysilicon resistor are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the polysilicon resistor are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Johann Christian Rode, Walid M. Hafez
  • Publication number: 20200219878
    Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a TFT provided over a second portion of the III-N material. Because the III-N transistor and the TFT are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the TFT are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration. Integrating TFTs with III-N transistors may reduce costs and improve performance, e.g., by reducing losses incurred when power is routed off chip in a multi-chip package.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200219986
    Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor, ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Glenn A. Glass, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200219772
    Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Applicant: INTEL CORPORATION
    Inventors: RAHUL RAMASWAMY, NIDHI NIDHI, WALID M. HAFEZ, JOHANN C. RODE, PAUL FISCHER, HAN WUI THEN, MARKO RADOSAVLJEVIC, SANSAPTAK DASGUPTA
  • Publication number: 20200219877
    Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N transistor provided in a first layer over a support structure (e.g., a substrate), and a TFT provided in a second layer over the support structure. The second layer is above the first layer, and, therefore, the III-N transistor and the TFT are “stacked” transistors. This way, one or more III-N transistors may be integrated with one or more TFTs, enabling monolithic integration of PMOS transistors, provided by TFTs, on a single chip with III-N NMOS transistors. Such integration may reduce costs and improve performance, e.g., by reducing RF losses incurred when power is routed off chip in a multi-chip package. Stacked arrangement of III-N transistors and TFTs provides a further advantage of reducing the total surface area occupied by these transistors.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
  • Patent number: 10707346
    Abstract: A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan
  • Publication number: 20200203484
    Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Johann C. RODE, Paul B. FISCHER, Walid M. HAFEZ
  • Patent number: 10692888
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Patent number: 10692771
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
  • Publication number: 20200194575
    Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Rahul RAMASWAMY, Nidhi NIDHI, Walid M. HAFEZ, Johann C. RODE, Paul FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA
  • Publication number: 20200194578
    Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Rahul RAMASWAMY, Nidhi NIDHI, Walid M. HAFEZ, Johann C. RODE, Paul FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Heli Chetanbhai VORA
  • Patent number: 10658361
    Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez
  • Patent number: 10643999
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
  • Publication number: 20200135865
    Abstract: A semiconductor device is proposed. The semiconductor device includes a group III-N semiconductor layer, an electrically insulating material layer located on the group III-N semiconductor layer, and a metal contact structure located on the electrically insulating material layer. An electrical resistance between the metal contact structure and the group III-N semiconductor layer through the electrically insulating material layer is smaller than 1*10?7? for an area of 1 mm2. Further, semiconductor devices including a low resistance contact structure, radio frequency devices, and methods for forming semiconductor devices are proposed.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200105881
    Abstract: Group-III nitride (III-N) tunnel devices with a device structure including multiple quantum wells. A bias voltage applied across first device terminals may align the band structure to permit carrier tunneling between a first carrier gas residing in a first of the wells to a second carrier gas residing in a second of the wells. A III-N tunnel device may be operable as a diode, or further include a gate electrode. The III-N tunnel device may display a non-linear current-voltage response with negative differential resistance, and be employed as a frequency mixer operable in the GHz and THz bands. In some examples, a GHz-THz input RF signal and local oscillator signal are coupled into a gate electrode of a III-N tunnel device biased within a non-linear regime to generate an output RF signal indicative of a frequency difference between the RF signal and a local oscillator signal.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Rahul Ramaswamy, Walid M. Hafez, Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Nidhi Nidhi
  • Publication number: 20200066897
    Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Walid M. HAFEZ, Roman W. OLAC-VAW, Joodong PARK, Chen-Guan LEE, Chia-Hong JAN, Everett S. CASSIDY-COMFORT