Patents by Inventor Walid M. Hafez

Walid M. Hafez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200066907
    Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Chia-Hong JAN, Walid M. HAFEZ, Hsu-Yu CHANG, Neville L. DIAS, Rahul RAMASWAMY, Roman W. OLAC-VAW, Chen-Guan LEE
  • Publication number: 20200066712
    Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.
    Type: Application
    Filed: September 29, 2016
    Publication date: February 27, 2020
    Inventors: Walid M. HAFEZ, Roman W. OLAC-VAW, Joodong PARK, Chen-Guan LEE, Chia-Hong JAN
  • Patent number: 10559688
    Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Chen-Guan Lee, Walid M. Hafez, Joodong Park, Chia-Hong Jan, Hsu-Yu Chang
  • Publication number: 20200043914
    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 6, 2020
    Applicant: INTEL CORPORATION
    Inventors: ROMAN W. OLAC-VAW, WALID M. HAFEZ, CHIA-HONG JAN, HSU-YU CHANG, NEVILLE L. DIAS, RAHUL RAMASWAMY, NIDHI NIDHI, CHEN-GUAN LEE
  • Patent number: 10505034
    Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Xiaodong Yang, Jui-Yen Lin, Kinyip Phoa, Nidhi Nidhi, Yi Wei Chen, Kun-Huan Shih, Walid M. Hafez, Curtis Tsai
  • Publication number: 20190348516
    Abstract: Disclosed herein are transistor arrangements with one or more FinFETs, where threshold voltage tuning of a given FinFET may be implemented by controlling the height of a work function (WF) material provided as a layer at least partially surrounding sidewalls of the upper-most portion of the fin of that FinFET. In some embodiments, such a control may be achieved as a part of forming a gate stack of a FinFET. In particular, a layer of a desired WF material may be deposited within an opening formed around a channel region of a fin as a part of forming the gate stack, and subsequently recessed to a desired height, where, for a given geometry and materials selection, the amount of WF material recess controls threshold voltage of the resulting FinFET. In this manner, different FinFETs in a single transistor arrangement may have different heights of their WF material layer.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Intel Corporation
    Inventors: Rahul Ramaswamy, Walid M. Hafez, Roman W. Olac-vaw
  • Publication number: 20190304902
    Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez
  • Publication number: 20190304893
    Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Vincent DORGAN, Jeffrey HICKS, Uddalak BHATTACHARYA, Zhanping CHEN, Walid M. HAFEZ
  • Publication number: 20190305112
    Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON
  • Publication number: 20190305111
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Sairam SUBRAMANIAN, Christopher KENYON, Sridhar GOVINDARAJU, Chia-Hong JAN, Mark LIU, Szuya S. LIAO, Walid M. HAFEZ
  • Publication number: 20190304840
    Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.
    Type: Application
    Filed: September 30, 2016
    Publication date: October 3, 2019
    Inventors: Chen-Guan LEE, Everett S. CASSIDY-COMFORT, Joodong PARK, Walid M. HAFEZ, Chia-Hong JAN, Rahul RAMASWAMY, Neville L. DIAS, Hsu-Yu CHANG
  • Publication number: 20190304971
    Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON, Sairam SUBRAMANIAN
  • Publication number: 20190296105
    Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 26, 2019
    Inventors: Walid M. HAFEZ, Chia-Hong JAN
  • Publication number: 20190296114
    Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 26, 2019
    Inventors: Gopinath BHIMARASETTI, Walid M. HAFEZ, Joodong PARK, Weimin HAN, Raymond E. COTNER, Chia-Hong JAN
  • Publication number: 20190287972
    Abstract: Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.
    Type: Application
    Filed: September 30, 2016
    Publication date: September 19, 2019
    Inventors: Walid M. HAFEZ, Roman W. OLAC-VAW, Chia-Hong JAN
  • Publication number: 20190287973
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe
  • Publication number: 20190245098
    Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.
    Type: Application
    Filed: December 13, 2016
    Publication date: August 8, 2019
    Inventors: Rahul RAMASWAMY, Hsu-Yu CHANG, Chia-Hong JAN, Walid M. HAFEZ, Neville L. DIAS, Roman W. OLAC-VAW, Chen-Guan LEE
  • Publication number: 20190237564
    Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.
    Type: Application
    Filed: December 12, 2016
    Publication date: August 1, 2019
    Inventors: Chia-Hong JAN, Walid M. HAFEZ, Neville L. DIAS, Rahul RAMASWAMY, Hsu-Yu CHANG, Roman W. OLAC-VAW, Chen-Guan LEE
  • Patent number: 10355093
    Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Gopinath Bhimarasetti, Walid M. Hafez, Joodong Park, Weimin Han, Raymond E. Cotner, Chia-Hong Jan
  • Patent number: 10355081
    Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan