Patents by Inventor Walid M. Hafez

Walid M. Hafez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190206980
    Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.
    Type: Application
    Filed: October 21, 2016
    Publication date: July 4, 2019
    Inventors: Chia-Hong JAN, Walid M. HAFEZ, Neville L. DIAS, Rahul RAMASWAMY, Hsu-Yu CHANG, Roman W. OLAC-VAW, Chen-Guan LEE
  • Patent number: 10340220
    Abstract: IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Chen-Guan Lee, Vadym Kapinus, Pei-Chi Liu, Joodong Park, Walid M. Hafez, Chia-Hong Jan
  • Patent number: 10340273
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
  • Publication number: 20190157153
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Inventors: Roman W. OLAC-VAW, Walid M. HAFEZ, Chia-Hong JAN, Pei-Chi LIU
  • Publication number: 20190123170
    Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.
    Type: Application
    Filed: June 28, 2016
    Publication date: April 25, 2019
    Inventors: Jui-Yen Lin, Chen-Guan Lee, Joodong Park, Walid M. Hafez, Kun-Huan Shih
  • Publication number: 20190123164
    Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Applicant: Intel Corporation
    Inventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
  • Patent number: 10263112
    Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Curtis Tsai, Jeng-Ya D. Yeh, Joodong Park
  • Publication number: 20190097057
    Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventors: Neville L. Dias, Chia-Hong Jan, Walid M. Hafez, Roman W. Olac-Vaw, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu
  • Patent number: 10229853
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
  • Patent number: 10229866
    Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Yi Wei Chen, Kinyip Phoa, Nidhi Nidhi, Jui-Yen Lin, Kun-Huan Shih, Xiaodong Yang, Walid M. Hafez, Curtis Tsai
  • Patent number: 10204999
    Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
  • Publication number: 20190027604
    Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 24, 2019
    Applicant: INTEL CORPORATION
    Inventors: CHEN-GUAN LEE, WALID M. HAFEZ, JOODONG PARK, CHIA-HONG JAN, HSU-YU CHANG
  • Publication number: 20190006279
    Abstract: IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.
    Type: Application
    Filed: August 26, 2015
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Chen-Guan Lee, Vadym Kapinus, Pei-Chi Liu, Joodong Park, Walid M. Hafez, Chia-Hong Jan
  • Patent number: 10164115
    Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Neville L. Dias, Chia-Hong Jan, Walid M. Hafez, Roman W. Olac-Vaw, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu
  • Patent number: 10158034
    Abstract: An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Nidhi Nidhi, Chia-Hong Jan, Walid M. Hafez, Yi Wei Chen
  • Publication number: 20180331098
    Abstract: An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Inventors: Leonard P. Guler, Gopinath Bhimarasetti, Vyom Sharma, Walid M. Hafez, Christopher P. Auth
  • Publication number: 20180323260
    Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.
    Type: Application
    Filed: December 23, 2015
    Publication date: November 8, 2018
    Inventors: Hsu-Yu CHANG, Neville L. DIAS, Walid M. HAFEZ, Chia-Hong JAN, Roman W. OLAC-VAW, Chen-Guan LEE
  • Patent number: 10115721
    Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Walid M. Hafez, Peter J Vandervoorn, Chia-Hong Jan
  • Patent number: 10103542
    Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Akm Ahsan, Walid M. Hafez
  • Patent number: 10096599
    Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez