Patents by Inventor Walid M. Hafez

Walid M. Hafez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10090304
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan, Jeng-Ya D. Yeh, Hsu-Yu Chang, Neville Dias, Chanaka Munasinghe
  • Publication number: 20180248039
    Abstract: A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 30, 2018
    Applicant: INTEL CORPORATION
    Inventors: WALID M. HAFEZ, CHIA-HONG JAN
  • Publication number: 20180226432
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 9, 2018
    Inventors: Walid M. HAFEZ, Jeng-Ya D. YEH, Curtis TSAI, Joodong PARK, Chia-Hong JAN, Gopinath BHIMARASETTI
  • Publication number: 20180218977
    Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.
    Type: Application
    Filed: March 26, 2018
    Publication date: August 2, 2018
    Applicant: INTEL CORPORATION
    Inventors: TING CHANG, CHIA-HONG JAN, WALID M. HAFEZ
  • Publication number: 20180197966
    Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.
    Type: Application
    Filed: July 17, 2015
    Publication date: July 12, 2018
    Applicant: Intel Corporation
    Inventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
  • Patent number: 10020313
    Abstract: An antifuse may include a non-planar conductive terminal having a high-z portion extending to a greater z-height than a low-z portion. A second conductive terminal is disposed over the low-z portion and separated from the first terminal by at least one intervening dielectric material. Fabrication of an antifuse may include forming a first opening in a first dielectric material disposed over a substrate, and undercutting a region of the first dielectric material. The undercut region of the first dielectric material is lined with a second dielectric material, such as gate dielectric material, through the first opening. A conductive first terminal material backfills the lined undercut region through the first opening. A second opening through the first dielectric material exposes the second dielectric material lining the undercut region. A conductive second terminal material is backfilled in the second opening.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: July 10, 2018
    Assignee: Intel Corporation
    Inventors: Chen Guan Lee, Walid M. Hafez, Chia Hong Jan
  • Patent number: 10008445
    Abstract: Embedded fuse structures and fabrication techniques. An embedded fuse may include a non-planar conductive line having two high-z portions extending to a greater z-height than a low-z portion of reduced current carrying capability disposed there between. A dielectric disposed over the low-z portion has a top surface planar with the high-z line portions to which fuse contacts may be landed. Fabrication of an embedded fuse may include undercutting a region of a first dielectric material disposed over a substrate. The undercut region is lined with a second dielectric material. A pair of electrically joined fuse ends are formed by backfilling the lined undercut region with a conductive material. In advantageous embodiments, fuse fabrication is compatible with high-K, metal gate transistor and precision polysilicon resistor fabrication flows.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventors: Chen-Guan Lee, Walid M. Hafez, Chia-Hong Jan
  • Patent number: 10002954
    Abstract: Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan
  • Publication number: 20180158906
    Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
    Type: Application
    Filed: January 31, 2018
    Publication date: June 7, 2018
    Inventors: Walid M. HAFEZ, Chia-Hong JAN
  • Publication number: 20180151474
    Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.
    Type: Application
    Filed: June 22, 2015
    Publication date: May 31, 2018
    Applicant: INTEL CORPORATION
    Inventors: YI WEI CHEN, KINYIP PHOA, NIDHI NIDHI, JUI-YEN LIN, KUN-HUAN SHIH, XIAODONG YANG, WALID M. HAFEZ, CURTIS TSAI
  • Publication number: 20180145083
    Abstract: The controlled modification of an antifuse programming voltage is described. In one example, an antifuse circuit is formed on a substrate, including a gate area of the antifuse circuit. A molecule is implanted into the gate area to damage the structure of the gate area. Electrodes are formed over the gate areas to connect the antifuse circuit to other components.
    Type: Application
    Filed: June 25, 2015
    Publication date: May 24, 2018
    Inventors: Xiaoghong TONG, Walid M. HAFEZ, Zhiyong MA, Peng BAI, Chia-Hong JAN, Zhanping CHEN
  • Patent number: 9972642
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Publication number: 20180130902
    Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.
    Type: Application
    Filed: June 19, 2015
    Publication date: May 10, 2018
    Inventors: Xiaodong YANG, Jui-Yen LIN, Kinyip PHOA, Nidhi NIDHI, Yi Wei CHEN, Kun-Huan SHIH, Walid M. HAFEZ, Curtis TSAI
  • Patent number: 9947585
    Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Chia-Hong Jan, Roman W. Olac-Vaw, Hsu-Yu Chang, Neville L. Dias, Walid M. Hafez, Rahul Ramaswamy
  • Patent number: 9929090
    Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1 T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: March 27, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ting Chang, Chia-Hong Jan, Walid M. Hafez
  • Patent number: 9911815
    Abstract: Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Chia-Hong Jan, Walid M. Hafez
  • Patent number: 9899472
    Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan
  • Publication number: 20180040637
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Application
    Filed: October 16, 2017
    Publication date: February 8, 2018
    Inventors: Walid M. HAFEZ, Jeng-Ya D. YEH, Curtis TSAI, Joodong PARK, Chia-Hong JAN, Gopinath BHIMARASETTI
  • Patent number: 9881927
    Abstract: CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Jeng-Ya D. Yeh, Chia-Hong Jan, Walid M. Hafez, Joodong Park
  • Patent number: 9865695
    Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan, Anisur Rahman