Patents by Inventor Walter Contrata

Walter Contrata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020171096
    Abstract: In a field effect transistor, there are provided a gate electrode on a Schottky layer over an InP channel layer over the substrate, and a field control electrode extending over an insulating layer and separated from the Schottky layer and being positioned between the gate electrode and the drain electrode for controlling an expansion of a space charge region in the channel layer.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 21, 2002
    Applicant: NEC CORPORATION
    Inventors: Akio Wakejima, Kazuki Ota, Kohji Matsunaga, Walter Contrata, Masaaki Kuzuhara
  • Publication number: 20020025664
    Abstract: There is formed, so as to cover the upper structure (a gold-containing, low-resistance metal layer) of a T- or Y-shaped gate, a thin film (e.g. a thin TiN film) which is not reactive to the low-resistance metal layer, which is resistant to an etching solution to be applied in a later wet etching step, and which has good adhesivity to a resist to be coated in a later step, to prevent the direct contact of the low-resistance metal layer with the resist. In this state, supports are formed.
    Type: Application
    Filed: August 24, 2001
    Publication date: February 28, 2002
    Applicant: NEC Corporation
    Inventors: Akio Wakejima, Norihiko Samoto, Walter Contrata
  • Patent number: 6172513
    Abstract: A Schottky contact of a heterojunction field effect transistor is expressed by a set of regional elements each representative of a line or a region of said Schottky contact, and current components respectively passing through the regional elements are expressed as I ⁡ ( R1 , R2 , ⋯ . , R N ) = ∑ k = 1 N ⁢ J k ⁢ R k where I is a gate current current, Rk is a length of the line or an area of the region, N is equal to or greater than 3 and Jk is a current density of one of the current components so that an analyst checks the current components to see whether or not the Schottky contact has a trouble.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: January 9, 2001
    Assignee: NEC Corporation
    Inventor: Walter Contrata
  • Patent number: 5943577
    Abstract: In a method manufacturing a semiconductor device, a semiconductor layer having a device forming region is formed on substrate. Next, a region except for the device forming region is changed into an insulator. In this case, a conducting path is left across the semiconductor device to electrically connect the semiconductor device with an adjacent semiconductor device. Subsequently, the device forming region is etched on the condition that the conducting path is left. Finally, the conducting path is disrupted after the etching process. Thus, the semiconductor device and the adjacent semiconductor device are left in an electrical contact via the conducting path during the etching process. Consequently, the uniformity of the etching between the semiconductor devices is largely improved.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: August 24, 1999
    Assignee: NEC Corporation
    Inventors: Walter Contrata, Naotaka Iwata