Patents by Inventor Walter D. Parmantie

Walter D. Parmantie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6048789
    Abstract: An integrated circuit manufacturing method uses chemical-mechanical polishing (CMP) to planarize a nonplanar submetal (or intermetal) silica dielectric layer. The planarized device is cleaned with an aqueous solution of ammonium hydroxide and citric acid. Exposed hydrated silica is etched using mixture of nitric and hydrofluoric acids, freeing embedded contaminants from the CMP slurry. The hydrofluroic acid is the etching agent, while the nitric acid combines with the freed contaminants to render water soluble products. They are thus carried away in an aqueous rinse, whereas otherwise they might recontaminate the device. A metal interconnect structure is formed on the etched oxide by forming contact apertures, depositing metal, and patterning the metal. The method can be applied also to nonplanar intermetal dielectrics and subsequent metal interconnect layers. The result is an integrated manufacturing method with higher yields and a more reliable manufactured integrated circuit.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: April 11, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Landon B. Vines, Craig A. Bellows, Walter D. Parmantie
  • Patent number: 5793094
    Abstract: A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: August 11, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Ivan Sanchez, Yu-Pin Han, Ying-Tsong Loh, Walter D. Parmantie
  • Patent number: 5493132
    Abstract: A titanium-tungsten barrier layer is sputtered after active areas of a CMOS structure are exposed. An ion implant through the barrier layer and into the active areas disrupts the boundaries between the barrier layer and the underlying active areas. The implant can involve argon or, alternatively, silicon. The resulting structure is annealed. A conductor layer of an aluminum-copper alloy is deposited. An antireflection coating of TiW is deposited. The three-layer structure is then photolithographically patterned to define contacts and local interconnects. The ion implant before anneal results in less contact resistance, which is particularly critical for the barrier layer boundary with positively doped active areas.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: February 20, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Hunter B. Brugge, Kuang-Yeh Chang, Felix Fujishiro, Chang-Ou Lee, Walter D. Parmantie
  • Patent number: 5395773
    Abstract: After gates are patterned in a submicron CMOS process, a halo implant is performed with sufficient energy that the halo implant penetrates the gate structures to below the transistor channel regions. Where the substrate is not masked by gate materal, the halo implant penetrates below drain and source regions. During diffusion, this halo limits lateral diffusion of the source/drain dopants. The resulting transistor exhibits enhanced breakdown voltage characteristics during both on and off conditions.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: March 7, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: K. S. Ravindhran, Yu P. Han, Ravi Jhota, Walter D. Parmantie