Patents by Inventor Walter Rieger

Walter Rieger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160035862
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Patent number: 9202909
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 1, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
  • Patent number: 9171841
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 27, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Patent number: 9142444
    Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 22, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zundel, Erwin Bacher, Andreas Behrendt, Joerg Ortner, Walter Rieger, Rudolf Zelsacher
  • Publication number: 20150256155
    Abstract: An electronic circuit includes a transistor arrangement with a plurality of transistor devices, each including a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel. The electronic circuit further includes a drive circuit coupled to the control node of each of the plurality of transistor devices, and configured to receive an input signal. Each of the plurality of transistor devices includes a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG. The drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate at least one of the plurality of transistor devices based on the load signal.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 10, 2015
    Inventors: Oliver Haeberlen, Walter Rieger
  • Publication number: 20150249020
    Abstract: Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1?0, y1?0, z1?0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2?0, z2?0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.
    Type: Application
    Filed: May 13, 2015
    Publication date: September 3, 2015
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Haeberlen, Walter Rieger, Christoph Kadow, Markus Zundel
  • Publication number: 20150243775
    Abstract: A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Applicant: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger
  • Publication number: 20150179643
    Abstract: One aspect relates to a semiconductor component with a semiconductor body, a first main contact pad, a second main contact pad, a normally-on first transistor monolithically integrated in the semiconductor body and a normally-off second transistor monolithically integrated in the semiconductor body. The first transistor is a high electron mobility transistor having a first gate electrode and a first load path controllable via a first gate electrode, and the second transistor has a second gate electrode and a second load path controllable via the second gate electrode. The first load path and the second load path are electrically connected in series between the first main contact pad and the second main contact pad.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Inventors: Gilberto Curatola, Oliver Haeberlen, Walter Rieger, Anthony Sanders
  • Patent number: 9041066
    Abstract: A transistor device includes a compound semiconductor body, a normally-on high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and a protection device monolithically integrated in the same compound semiconductor body as the normally-on HEMT. The normally-on HEMT has a source, a drain, a gate, and a threshold voltage. The protection device has a source and a drain each shared with the normally-on HEMT, a gate and a positive threshold voltage that is less than a difference of the threshold voltage of the normally-on HEMT and a gate voltage used to turn off the normally-on HEMT. The protection device is operable to conduct current in a reverse direction when the normally-on HEMT is switched off. A transistor device including a normally-off HEMT and a monolithically integrated protection device is also provided.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Walter Rieger, Oliver Häberlen
  • Patent number: 8946767
    Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Sonja Krumrey
  • Patent number: 8907340
    Abstract: A semiconductor arrangement includes a semiconductor body and a semiconductor device, the semiconductor device including first and second load terminals arranged distant to each other in a first direction of the semiconductor body and a load path arranged in the semiconductor body between the first and second load terminals. The semiconductor arrangement further includes at least one Hall sensor arranged in the semiconductor body distant to the semiconductor device in a second direction perpendicular to the first direction. The Hall sensor includes two current supply terminals and two measurement terminals.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 9, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Lutz Goergens, Helmut Angerer, Gianmauro Pozzovivo, Markus Zundel
  • Publication number: 20140346569
    Abstract: A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
  • Patent number: 8884335
    Abstract: A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Markus Zundel
  • Publication number: 20140319602
    Abstract: A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal.
    Type: Application
    Filed: April 30, 2013
    Publication date: October 30, 2014
    Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
  • Publication number: 20140284702
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Application
    Filed: June 5, 2014
    Publication date: September 25, 2014
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Publication number: 20140264577
    Abstract: A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Walter Rieger, Hans Weber, Michael Treu, Gerhard Nöbauer, Martin Pölzl, Martin Vielemeyer, Franz Hirler
  • Patent number: 8759905
    Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Thorsten Meyer, Wolfgang Klein, Frank Pfirsch
  • Patent number: 8652906
    Abstract: A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: February 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Walter Rieger, Markus Zundel
  • Publication number: 20140035003
    Abstract: A transistor device includes a compound semiconductor body, a normally-on high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and a protection device monolithically integrated in the same compound semiconductor body as the normally-on HEMT. The normally-on HEMT has a source, a drain, a gate, and a threshold voltage. The protection device has a source and a drain each shared with the normally-on HEMT, a gate and a positive threshold voltage that is less than a difference of the threshold voltage of the normally-on HEMT and a gate voltage used to turn off the normally-on HEMT. The protection device is operable to conduct current in a reverse direction when the normally-on HEMT is switched off. A transistor device including a normally-off HEMT and a monolithically integrated protection device is also provided.
    Type: Application
    Filed: October 16, 2013
    Publication date: February 6, 2014
    Applicant: Infineon Technologies Austria AG
    Inventors: Walter Rieger, Oliver Häberlen
  • Publication number: 20140021637
    Abstract: A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.
    Type: Application
    Filed: September 25, 2013
    Publication date: January 23, 2014
    Applicant: Infineon Technologies AG
    Inventors: Walter Rieger, Franz Hirler, Martin Poelzl, Manfred Kotek