Patents by Inventor Walter T. Matzen

Walter T. Matzen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6492697
    Abstract: A Hall-effect element includes an isolating layer and an active layer of a first electrical conductivity type disposed on the isolating layer, the active layer having a surface. A first set of contacts is disposed in contact with the surface along a first axis, and a second set of contacts is disposed in contact with the surface along a second axis transverse to the first axis. An insulating layer is disposed on the surface. A metal control field plate is disposed on the insulating layer and is coupleable to a voltage source to control the accumulation of charge carriers at the surface of the active layer to vary the resistance of the active layer. Also, a method is provided for reducing null offset in a Hall-effect element.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: December 10, 2002
    Assignee: Honeywell International Inc.
    Inventors: Mark R. Plagens, Michael J. Haji-Sheikh, Walter T. Matzen
  • Patent number: 6069905
    Abstract: A vertical cavity surface emitting laser having intensity control for maintaining a constant proportional output under varying conditions of the laser. A tilted window is situated over the laser output to reflect a portion of the light to a photo detector area. Signals representing light on the photo detector go to a feedback circuit which controls the power output of the laser. The tilted window has a metallic coating for partial reflection and for minimizing polarization effects on reflected and transmitted light. The photo detector has an anti-reflective coating for likewise minimizing polarization effects of the detected light. The VCSEL and photo detector are situated on the same substrate.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: May 30, 2000
    Assignee: Honeywell Inc.
    Inventors: Richard A Davis, Walter T. Matzen, James K. Guenter, David Smith
  • Patent number: 5466954
    Abstract: A phototransistor is provided with a first resistor that operates as a shunt and a second resistor that operates to protect the device from damage that could be caused by a reverse bias condition. The possible damage results from the creation of a PN junction relationship caused by the doping of N conductivity type material with P.sup.+ conductivity type material in order to form the first resistor. This junction relationship creates a parasitic diode that provides a current path between the emitter and collector terminals of the phototransistor. In order to prevent damage that might occur during a reverse voltage connection, a second resistor is connected between the emitter of transistor Q.sub.1 and the first resistor. The second resistor is in series with the junction relationship resulting from the structure used to form the first resistor and therefore serves to limit the current flowing between the emitter and collector terminals of the transistor under reversed bias conditions.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: November 14, 1995
    Assignee: Honeywell Inc.
    Inventors: Jose J. Aizpuru, Walter T. Matzen
  • Patent number: 5130760
    Abstract: A semiconductor device is provided for use as a bidirectional surge suppressor circuit. It incorporates doped regions of substrate and epitaxial layers which result in a dual Zener diode arrangement having the Zener diodes associated in an opposite polarity arrangement. The semiconductor device comprises a substrate with an epitaxial layer deposited on one of its surfaces. In an upper surface of the epitaxial layer, first and second regions of P type material are diffused with guard rings comprising P+ type material diffused around the first and second regions. The guard rings are heavily doped and extend much deeper than the relatively shallow junctions of P material. A channel stopper of N+ conductivity type material is diffused into the upper surface of the epitaxial layer to provide a channel stopper, or sinker, around both the first and second regions and their associated guard rings and, additionally, between the first and second regions.
    Type: Grant
    Filed: June 11, 1991
    Date of Patent: July 14, 1992
    Assignee: Honeywell Inc.
    Inventors: Walter T. Matzen, Ronald B. Foster
  • Patent number: 4658282
    Abstract: A semiconductor junction related structure to control sensitivity of signal processing systems to signals of greater versus smaller values.
    Type: Grant
    Filed: June 28, 1984
    Date of Patent: April 14, 1987
    Assignee: Honeywell Inc.
    Inventor: Walter T. Matzen, Jr.
  • Patent number: 4131983
    Abstract: A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.
    Type: Grant
    Filed: January 10, 1977
    Date of Patent: January 2, 1979
    Assignee: Texas Instruments Incorporated
    Inventor: Walter T. Matzen
  • Patent number: 4017885
    Abstract: Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate by orientation dependent etches and utilizing the sidewalls of the grooves as surface. Groove depth is limited to a predetermined value by etching time, geometrical constraints, or by etch stops. This provides for precise control of capacitance values on a batch or commercial basis. Increases up to at least 100-fold in capacitance as compared to a flat capacitor structure as possible. A thin layer of dielectric is formed over the increased surface area, and thereafter a conducting layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may also be formed.
    Type: Grant
    Filed: December 13, 1974
    Date of Patent: April 12, 1977
    Assignee: Texas Instruments Incorporated
    Inventors: Don L. Kendall, Walter T. Matzen
  • Patent number: 3982266
    Abstract: An integrated injection logic (IIL) structure including active devices, one of which is a switching transistor having base current injection from another active device where an epitaxial zone forms an emitter-base junction. A diffused zone in the epitaxial layer forms a collector for the switching transistor and an insulating structure defines perimeters of the collector-base junction and the emitter-base junction such that the widths thereof are about equal for maximizing current gain with minimal temperature dependence.
    Type: Grant
    Filed: December 9, 1974
    Date of Patent: September 21, 1976
    Assignee: Texas Instruments Incorporated
    Inventors: Walter T. Matzen, Wilton L. Workman
  • Patent number: 3962713
    Abstract: Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate and utilizing the sidewalls of the grooves as surface. A thin layer of dielectric is formed over the increased surface area, and thereafter a metal layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may be formed instead of a dielectric capacitor by forming a P-N junction comprising the increased surface area, and thereover forming the metallized contact.
    Type: Grant
    Filed: October 25, 1973
    Date of Patent: June 8, 1976
    Assignee: Texas Instruments Incorporated
    Inventors: Don L. Kendall, Walter T. Matzen
  • Patent number: 3936789
    Abstract: A spreading-resistance silicon thermistor having high-precision values of resistance and temperature coefficient of resistance (TCR) is produced by a high-volume, low-cost, photolithographic technique, wherein multiple thin-film contacts are tested and selectively trimmed to permit computerized control of precision resistance values in a production-line operation.
    Type: Grant
    Filed: June 3, 1974
    Date of Patent: February 3, 1976
    Assignee: Texas Instruments Incorporated
    Inventors: Walter T. Matzen, Don L. Kendall