Patents by Inventor Wanli Ma

Wanli Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220158834
    Abstract: Provided are a method and device employing a smart contract to realize identity-based key management. The method comprises: running a smart contract, and executing a key management process, wherein the key management process comprises: when a key of a target user requires an update and the target user is not a supervised user, generating a master public key and a master private key pertaining to the target user; acquiring, from a blockchain, identity information of the target user; generating a first target private key according to the master public key and the master private key pertaining to the target user and the identity information of the target user; and replacing a current private key of the target user with the first target private key.
    Type: Application
    Filed: June 18, 2019
    Publication date: May 19, 2022
    Inventors: Dongwei YANG, Dong WANG, Wei JIANG, Ping ZHEN, Jiaxing XUAN, Guomin LI, Xin SHI, Wanli MA, Junwei MA, Yang WANG, Lei ZHOU
  • Publication number: 20210047626
    Abstract: The present invention relates to a scalable process for the purification of human cytomegalovirus particles from cell culture medium. In particular, the process involves a two step chromatography process starting with an anion exchange chromatography step followed by a polishing chromatography step selected from mixed mode chromatography or cation exchange chromatography.
    Type: Application
    Filed: April 18, 2019
    Publication date: February 18, 2021
    Applicant: Merck Sharp & Dohme Corp.
    Inventors: Adam Kristopeit, Janelle Konieizko, Wanli Ma, Katie Phillips, Andrew Swartz, Sheng-Ching Wang, Marc D. Wenger, Matthew Woodling, Tiago Matos
  • Patent number: 10407065
    Abstract: A method, a device and an apparatus for planning a vehicle speed are provided. The method includes: determining initial planning speeds at a target path point and a reference path point based on curvature radiuses of a target front road and a reference front road, such that first and second lateral accelerations are not greater than a lateral acceleration threshold; and determining a target longitudinal acceleration and a target planning speed at the target path point based on the initial planning speeds at the target path point and the reference path point and a reference journey, such that the target longitudinal acceleration is in a defined range. Therefore, a vehicle can drive based on the target planning speed and the target longitudinal acceleration at the target path point, thereby avoiding drastic deceleration and lateral offset, improving driving safety of the vehicle and riding comfort and saving energy.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: September 10, 2019
    Assignees: NEUSOFT CORPORATION, NEUSOFT REACH AUTOMOTIVE TECHNOLOGY (SHANGHAI) CO., LTD
    Inventors: Wei Liu, Cheng Chi, Guangsheng Zhang, Lu Wei, Wanli Ma
  • Publication number: 20180186373
    Abstract: A method, a device and an apparatus for planning a vehicle speed are provided. The method includes: determining initial planning speeds at a target path point and a reference path point based on curvature radiuses of a target front road and a reference front road, such that first and second lateral accelerations are not greater than a lateral acceleration threshold; and determining a target longitudinal acceleration and a target planning speed at the target path point based on the initial planning speeds at the target path point and the reference path point and a reference journey, such that the target longitudinal acceleration is in a defined range. Therefore, a vehicle can drive based on the target planning speed and the target longitudinal acceleration at the target path point, thereby avoiding drastic deceleration and lateral offset, improving driving safety of the vehicle and riding comfort and saving energy.
    Type: Application
    Filed: June 9, 2017
    Publication date: July 5, 2018
    Applicants: NEUSOFT CORPORATION, NEUSOFT REACH AUTOMOTIVE TECHNOLOGY (SHANGHAI) CO. LTD.
    Inventors: Wei Liu, Cheng Chi, Guangsheng Zhang, Lu Wei, Wanli Ma
  • Patent number: 9490315
    Abstract: The invention provides a power semiconductor device and a method of fabricating the same and a cutoff ring. A cutoff ring located at a periphery of an active area of the power semiconductor device is etched forming at least one trench below which an implant area is formed by implanting ions into the trench, and a silicon dioxide dielectric layer covering the trench and a surface of the active area, are formed. Since the ions are implanted into the trench formed by etching the cutoff ring to thereby increase a depth of the implanted ions and a density of the cutoff ring, a width of the cutoff ring can be shortened to thereby address the technical problem of a considerable area of a chip occupied by the cutoff ring and improve a utilization ratio of the area of the chip so as to lower a cost of fabricating the chip.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: November 8, 2016
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventors: Li Li, Wanli Ma, Shengzhe Zhao
  • Patent number: 9136127
    Abstract: The invention discloses a method of fabricating a GOI silicon wafer, a GOI silicon wafer, and a method of GOI detection on the fabricated GOI silicon wafer, where the method of fabricating a GOI silicon wafer includes: in a process of fabricating a trench-type VDMOS, after a trench is formed and a gate oxide layer is grown, a poly-silicon layer is grown; and after the poly-silicon layer is grown, a mask of a metal layer is aligned with a silicon substrate with the poly-silicon layer grown, where the mask of the metal layer is a mask used in formation of the metal layer in the process of fabricating the VDMOS; and at least one pattern for GOI detection is formed on the silicon substrate with the poly-silicon layer grown, through the aligned mask of the metal layer in a photo-lithography to form a GOI silicon wafer.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: September 15, 2015
    Assignees: PEKING UNIVERSITY FOUNDER GROUP CO., LTD., FOUNDER MICROELECTRONICS INTERNATIONAL CO., LTD.
    Inventors: Wanli Ma, Wenkui Zhao
  • Publication number: 20150214295
    Abstract: The invention provides a power semiconductor device and a method of fabricating the same and a cutoff ring. A cutoff ring located at a periphery of an active area of the power semiconductor device is etched forming at least one trench below which an implant area is formed by implanting ions into the trench, and a silicon dioxide dielectric layer covering the trench and a surface of the active area, are formed. Since the ions are implanted into the trench formed by etching the cutoff ring to thereby increase a depth of the implanted ions and a density of the cutoff ring, a width of the cutoff ring can be shortened to thereby address the technical problem of a considerable area of a chip occupied by the cutoff ring and improve a utilization ratio of the area of the chip so as to lower a cost of fabricating the chip.
    Type: Application
    Filed: January 12, 2015
    Publication date: July 30, 2015
    Inventors: Li LI, Wanli MA, Shengzhe ZHAO
  • Patent number: 9017766
    Abstract: Methods, compositions and articles of manufacture involving soluble conjugated polymers are provided. The conjugated polymers have a sufficient density of polar substituents to render them soluble in a polar medium, for example water and/or methanol. The conjugated polymer may desirably comprise monomers which alter its conductivity properties. In some embodiments, the inventors have provided cationic conjugated polymers (CCPs) comprising both solubilizing groups and conductive groups, resulting in conductive conjugated polymers soluble in polar media. The different solubility properties of these polymers allow their deposition in solution in multilayer formats with other conjugated polymers. Also provided are articles of manufacture comprising multiple layers of conjugated polymers having differing solubility characteristics. Embodiments of the invention are described further herein.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: April 28, 2015
    Assignee: The Regents of the University of California
    Inventors: Guillermo C. Bazan, Bin Liu, Xiong Gong, Alan J. Heeger, Wanli Ma, Parameswar K. Iyer
  • Patent number: 8795781
    Abstract: Methods, compositions and articles of manufacture involving soluble conjugated polymers are provided. The conjugated polymers have a sufficient density of polar substituents to render them soluble in a polar medium, for example water and/or methanol. The conjugated polymers may desirably comprise monomers which alter their conductivity properties. The different solubility properties of these polymers allow their deposition in solution in multilayer formats with other conjugated polymers. Also provided are articles of manufacture comprising multiple layers of conjugated polymers having differing solubility characteristics. Embodiments of the invention are described further herein.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: August 5, 2014
    Assignee: The Regents of the University of California
    Inventors: Guillermo C. Bazan, Alan J. Heeger, Parameswar K. Iyer, Bin Liu, Xiong Gong, Wanli Ma
  • Publication number: 20140209906
    Abstract: The invention discloses a method of fabricating a GOI silicon wafer, a GOI silicon wafer, and a method of GOI detection on the fabricated GOI silicon wafer, where the method of fabricating a GOI silicon wafer includes: in a process of fabricating a trench-type VDMOS, after a trench is formed and a gate oxide layer is grown, a poly-silicon layer is grown; and after the poly-silicon layer is grown, a mask of a metal layer is aligned with a silicon substrate with the poly-silicon layer grown, where the mask of the metal layer is a mask used in formation of the metal layer in the process of fabricating the VDMOS; and at least one pattern for GOI detection is formed on the silicon substrate with the poly-silicon layer grown, through the aligned mask of the metal layer in a photo-lithography to form a GOI silicon wafer.
    Type: Application
    Filed: November 29, 2013
    Publication date: July 31, 2014
    Applicants: Founder Microelectronics International Co., Ltd., Peking University Founder Group Co. Ltd.
    Inventors: Wanli Ma, Wenkui Zhao
  • Patent number: 8309672
    Abstract: Methods, compositions and articles of manufacture involving soluble conjugated polymers are provided. The conjugated polymers have a sufficient density of polar substituents to render them soluble in a polar medium, for example water and/or methanol. The conjugated polymer may desirably comprise monomers which alter its conductivity properties. In some embodiments, the inventors have provided cationic conjugated polymers (CCPs) comprising both solubilizing groups and conductive groups, resulting in conductive conjugated polymers soluble in polar media. The different solubility properties of these polymers allow their deposition in solution in multilayer formats with other conjugated polymers. Also provided are articles of manufacture comprising multiple layers of conjugated polymers having differing solubility characteristics. Embodiments of the invention are described further herein.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: November 13, 2012
    Assignee: The Regents of the University of California
    Inventors: Guillermo C. Bazan, Bin Liu, Xiong Gong, Alan J. Heeger, Wanli Ma, Parameswar K. Iyer
  • Patent number: 8227691
    Abstract: Processing additives, as well as related compositions, photovoltaic cells, photovoltaic modules, and methods, are disclosed.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: July 24, 2012
    Assignee: The Regents of the University of California
    Inventors: Guillermo Bazan, Christoph Brabec, Russell Gaudiana, Alan J. Heeger, Markus Koppe, Jae Kwan Lee, Wanli Ma, Mauro Morana, Markus Scharber, David Waller
  • Publication number: 20110277838
    Abstract: The present invention provides a photovoltaic device. In an exemplary embodiment, the photovoltaic device includes a substrate having a thin film disposed thereon, where the thin film includes alloyed ternary nanocrystals. The present invention provides also provides a method of making ternary compound nanocrystals. In an exemplary embodiment, the method includes (1) degassing a solution of PbO, oleic acid and 1-octadecene (ODE) in a container, (2) heating the solution in the container, (3) injecting a first mixture of trioctylphosphine (TOP):Se solution, TMS2S, diphenylphosphine (DPP) and ODE into the heated solution, thereby forming a second mixture in the container, (4) adding ODE to the second mixture in the container, (5) growing the nanocrystals in the second mixture in a reaction in the container, and (6)_quenching the reaction, thereby resulting in precipitated nanocrystals in the container. In a further embodiment, the present invention further includes purifying the precipitated nanocrystals.
    Type: Application
    Filed: March 11, 2011
    Publication date: November 17, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Wanli Ma, A. Paul Alivisatos
  • Patent number: 7830085
    Abstract: White light-emitting electrophosphorescent polymeric light-emitting diodes (PLEDs) are demonstrated using semiconducting polymers blended with organometallic emitters as emissive materials in a common region. These materials may be cast from solution. The CIE coordinates, the color temperatures and the color rendering indices of the white emission are insensitive to the brightness, applied voltage and applied current density.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: November 9, 2010
    Assignee: The Regents of the University of California
    Inventors: Xiong Gong, Wanli Ma, Jacek Ostrowski, Guillermo C. Bazan, Daniel Moses, Alan J. Heeger
  • Publication number: 20090108255
    Abstract: Processing additives, as well as related compositions, photovoltaic cells, photovoltaic modules, and methods, are disclosed.
    Type: Application
    Filed: October 23, 2008
    Publication date: April 30, 2009
    Inventors: Guillermo Bazan, Christoph Brabec, Russell Gaudiana, Alan J. Heeger, Markus Koppe, Jae Kwan Lee, Wanli Ma, Mauro Morana, Markus Scharber, David Waller
  • Publication number: 20050073245
    Abstract: White light-emitting electrophosphorescent polymeric light-emitting diodes (PLEDs) are demonstrated using semiconducting polymers blended with organometallic emitters as emissive materials in a common region. These materials may be cast from solution. The CIE coordinates, the color temperatures and the color rendering indices of the white emission are insensitive to the brightness, applied voltage and applied current density.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 7, 2005
    Inventors: Xiong Gong, Wanli Ma, Jacek Ostrowski, Guillermo Bazan, Daniel Moses, Alan Heeger