Patents by Inventor Wan Suk Oh

Wan Suk Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250029868
    Abstract: Provided is a substrate processing apparatus. The substrate processing apparatus includes a chamber in which a process with respect to a substrate is performed, a susceptor which is installed in the chamber and on which the substrate is placed, a plurality of lift pins passing through the susceptor to support the substrate, and a plurality of protection plugs protruding from a bottom surface of the susceptor to surround a portion of each of the lift pins protruding from the bottom surface of the susceptor.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 23, 2025
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Doo Yeol RYU, Ho Min CHOI, Wan Suk OH, Sung Gyun SON, Hyo Jin AHN, Sang Don LEE, Woo Young KANG, Se Yeong KIM, Ki Ho KIM, Koon Woo LEE
  • Publication number: 20230097999
    Abstract: According to an embodiment of the present invention, a substrate processing apparatus including: a chamber in which a process is performed on a substrate; a susceptor installed in the chamber to support the substrate; and a showerhead installed above the susceptor, and the showerhead includes: a plurality of inner injection holes defined in an inner area corresponding to a portion above the substrate and injecting a reaction gas downward; and a plurality of outer injection holes defined in an outer area corresponding to a portion outside the inner area and injecting an inert gas along an inner wall of the chamber.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 30, 2023
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Doo-Yeol RYU, Sang Don LEE, Wan Suk OH, Ho Min CHOI, Sung Gyun SON, Hyo Jin AHN
  • Publication number: 20220049349
    Abstract: According to an embodiment of the present invention, a method for forming a thin film includes loading an object to be processed into a chamber, and while controlling the temperature of the object to be processed to be 400° C. or less, supplying an Si source gas and an oxidizing gas into the chamber to form a silicon oxide film on the surface of the object to be processed, wherein the oxidizing gas is heated to a temperature exceeding 400° C. before being supplied into the chamber.
    Type: Application
    Filed: September 9, 2019
    Publication date: February 17, 2022
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Jin Woong KIM, Seung Woo SHIN, Cha Young YOO, Woo Duck JUNG, Doo Yeol RYU, Sung Kil CHO, Ho Min CHOI, Wan Suk OH, Koon Woo LEE, Ki Ho KIM
  • Patent number: 10796915
    Abstract: Provided is a method for forming an epitaxial layer at a low temperature. The method for forming the epitaxial layer includes transferring a substrate into an epitaxial chamber and performing an epitaxial process on the substrate to form an epitaxial layer on the substrate. The epitaxial process includes heating the substrate at a temperature of about 700° C. or less and injecting a silicon gas into the epitaxial chamber in a state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a first epitaxial layer, stopping the injection of the silicon gas and injecting a purge gas into the epitaxial chamber to perform first purge inside the epitaxial chamber, heating the substrate at a temperature of about 700° C.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 6, 2020
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Doo Yeol Ryu, Seung Woo Shin, Cha Young Yoo, Woo Duck Jung, Ho Min Choi, Wan Suk Oh, Hui Sik Kim, Eun Ho Kim, Seong Jin Park
  • Publication number: 20190304785
    Abstract: Provided is a method for forming an epitaxial layer at a low temperature. The method for forming the epitaxial layer includes transferring a substrate into an epitaxial chamber and performing an epitaxial process on the substrate to form an epitaxial layer on the substrate. The epitaxial process includes heating the substrate at a temperature of about 700° C. or less and injecting a silicon gas into the epitaxial chamber in a state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a first epitaxial layer, stopping the injection of the silicon gas and injecting a purge gas into the epitaxial chamber to perform first purge inside the epitaxial chamber, heating the substrate at a temperature of about 700° C.
    Type: Application
    Filed: August 14, 2017
    Publication date: October 3, 2019
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Doo Yeol RYU, Seung Woo SHIN, Cha Young YOO, Woo Duck JUNG, Ho Min CHOI, Wan Suk OH, Hui Sik KIM, Eun Ho KIM, Seong Jin PARK
  • Patent number: 10246773
    Abstract: A method for forming an amorphous thin film comprises: forming a seed layer on a surface of a base by supplying aminosilane-based gas on the base; forming the first boron-doped amorphous thin film by supplying the first source gas including boron-based gas on the seed layer; and forming the second boron-doped amorphous thin film by supplying the second source gas including boron-based gas on the first amorphous thin film.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: April 2, 2019
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo Shin, Cha-Young Yoo, Woo-Duck Jung, Ho-Min Choi, Wan-Suk Oh, Koon-Woo Lee, Hyuk-Lyong Gwon, Ki-Ho Kim
  • Patent number: 10006121
    Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: June 26, 2018
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
  • Publication number: 20180112307
    Abstract: According to an embodiment of the present invention, provided is a method for forming an amorphous thin film, the method comprising: forming a seed layer on a surface of a base by supplying aminosilane-based gas on the base; forming the first boron-doped amorphous thin film by supplying the first source gas including boron-based gas on the seed layer; and forming the second boron-doped amorphous thin film by supplying the second source gas including boron-based gas on the first amorphous thin film.
    Type: Application
    Filed: May 9, 2016
    Publication date: April 26, 2018
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo SHIN, Cha-young YOO, Woo-Duck JUNG, Ho-Min CHOI, Wan-Suk OH, Koon-Woo LEE, Hyuk-Lyong GWON, Ki-Ho KIM
  • Publication number: 20170256410
    Abstract: Provided is a method and apparatus for depositing an amorphous silicon film. The method includes supplying a source gas and an atmospheric gas onto a substrate in a state where the substrate is loaded in a chamber to deposit the amorphous silicon film on the substrate. The atmospheric gas includes at least one of hydrogen and helium. The source gas includes at least one of silane (SiH2), disilane (Si2H6), and dichlorosilane (SiCl2H2).
    Type: Application
    Filed: May 18, 2017
    Publication date: September 7, 2017
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo SHIN, Hai-Won KIM, Woo-Duck JUNG, Sung-Kil CHO, Wan-Suk OH, Ho-Min CHOI, Koon-Woo LEE
  • Patent number: 9741562
    Abstract: Provided is a method for forming a silicon film, and more particularly, to a method for forming a polycrystalline silicon film including pretreatment process in a process for forming a silicon film. According to an embodiment of the present invention, a method for forming a polycrystalline silicon film by annealing a amorphous silicon film deposited on a base, the method includes a pretreatment process of allowing a pretreatment gas including at least one of N, C, O and B to flow.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: August 22, 2017
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo Shin, Woo Duck Jung, Sung-Kil Cho, Ho Min Choi, Wan Suk Oh, Koon Woo Lee, Hyuk Lyong Gwon, Seong Jin Park, Ki Ho Kim, Kang-Wook Lee
  • Patent number: 9721798
    Abstract: Provided is a method and apparatus for depositing an amorphous silicon film. The method includes supplying a source gas and an atmospheric gas onto a substrate in a state where the substrate is loaded in a chamber to deposit the amorphous silicon film on the substrate. The atmospheric gas includes at least one of hydrogen and helium. The source gas includes at least one of silane (SiH2), disilane (Si2H6), and dichlorosilane (SiCl2H2).
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 1, 2017
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo Shin, Hai-Won Kim, Woo-Duck Jung, Sung-Kil Cho, Wan-Suk Oh, Ho-Min Choi, Koon-Woo Lee
  • Publication number: 20170178906
    Abstract: Provided is a method for forming a silicon film, and more particularly, to a method for forming a polycrystalline silicon film including pretreatment process in a process for forming a silicon film. According to an embodiment of the present invention, a method for forming a polycrystalline silicon film by annealing a amorphous silicon film deposited on a base, the method includes a pretreatment process of allowing a pretreatment gas including at least one of N, C, O and B to flow.
    Type: Application
    Filed: January 27, 2015
    Publication date: June 22, 2017
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo SHIN, Woo Duck JUNG, Sung-kil CHO, Ho Min CHOI, Wan Suk OH, Koon Woo LEE, Hyuk-Lyong GWON, Seong Jin PARK, Ki Ho KIM, Kang-Wook LEE
  • Patent number: 9425057
    Abstract: A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and the step for laminating the sacrificial layer includes a step for depositing a second silicon oxide film by supplying dichlorosilane (SiCl2H2) to the substrate.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: August 23, 2016
    Assignee: Eugene Technology Co., Ltd.
    Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
  • Publication number: 20160211141
    Abstract: Provided is a method and apparatus for depositing an amorphous silicon film. The method includes supplying a source gas and an atmospheric gas onto a substrate in a state where the substrate is loaded in a chamber to deposit the amorphous silicon film on the substrate. The atmospheric gas includes at least one of hydrogen and helium. The source gas includes at least one of silane (SiH2), disilane (Si2H6), and dichlorosilane (SiCl2H2).
    Type: Application
    Filed: September 15, 2014
    Publication date: July 21, 2016
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo SHIN, Hai-Won KIM, Woo-Duck JUNG, Sung-Kil CHO, Wan-Suk OH, Ho-Min CHOI, Koon-Woo LEE
  • Patent number: 9396954
    Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: July 19, 2016
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
  • Publication number: 20140261186
    Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 18, 2014
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Sung Kil CHO, Hai Won KIM, Sang Ho WOO, Seung Woo SHIN, Gil Sun JANG, Wan Suk OH
  • Publication number: 20130178066
    Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.
    Type: Application
    Filed: October 6, 2011
    Publication date: July 11, 2013
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
  • Publication number: 20130171827
    Abstract: A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and the step for laminating the sacrificial layer includes a step for depositing a second silicon oxide film by supplying dichlorosilane (SiCl2H2) to the substrate.
    Type: Application
    Filed: October 6, 2011
    Publication date: July 4, 2013
    Applicant: Eugene Technology Co., Ltd.
    Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
  • Publication number: 20120160419
    Abstract: A substrate-supporting unit includes: a mounting board on which a substrate is disposed; and a heater installed in the mounting board to heat the substrate disposed on the mounting board, wherein the mounting board includes: a non-contact surface which faces a center portion of the substrate and is spaced apart from the center portion of the substrate; and a contact member which extends outward from the non-contact surface and is arranged along an edge portion of the substrate disposed on the mounting board to support the edge portion of the substrate.
    Type: Application
    Filed: April 12, 2010
    Publication date: June 28, 2012
    Inventors: Dong-Keun Lee, Sergey Zaretskiy, Sung Tae Je, Wan Suk Oh