Patents by Inventor Wan Sup Shin
Wan Sup Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250063717Abstract: A method for fabricating a semiconductor device includes forming a stack body by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer over a lower structure; forming an opening in the stack body; forming a capping layer that exposes an edge of the third layer by horizontally recessing the second layer and the fourth layer from the opening; forming a liner structure on the capping layer and an edge of the third layer; forming a sacrificial liner material over the liner structure; recessing the sacrificial liner material and the liner structure to expose an edge of the third layer; forming a third layer pattern by recessing an exposed edge of the third layer; and forming a data storage element that is coupled to the third layer pattern.Type: ApplicationFiled: February 23, 2024Publication date: February 20, 2025Inventors: Bo Min PARK, Wan Sup SHIN, Seung Mi YEO
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Publication number: 20240349488Abstract: A semiconductor memory device includes: a conductive line stack including a plurality of first conductive lines that are stacked over a substrate in a direction perpendicular to a surface of the substrate; conductive pads extending laterally from edge portions of the first conductive lines, respectively; and contact plugs coupled to the conductive pads, respectively.Type: ApplicationFiled: June 24, 2024Publication date: October 17, 2024Inventors: Seung Wook RYU, Wan Sup SHIN
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Publication number: 20240292633Abstract: A semiconductor device may include a peripheral circuit portion, a memory cell array disposed over the peripheral circuit portion and including a vertical conductive line, a bonding pad structure between the peripheral circuit portion and the memory cell array, a dielectric pad layer configured to cover the top of the vertical conductive line of the memory cell array, and a higher-level pad that is coupled to the vertical conductive line through the dielectric pad layer.Type: ApplicationFiled: August 28, 2023Publication date: August 29, 2024Inventors: Il Do KIM, Wan Sup SHIN, Jae Sun SONG
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Patent number: 12048144Abstract: A semiconductor memory device includes: a conductive line stack including a plurality of first conductive lines that are stacked over a substrate in a direction perpendicular to a surface of the substrate; conductive pads extending laterally from edge portions of the first conductive lines, respectively; and contact plugs coupled to the conductive pads, respectively.Type: GrantFiled: June 14, 2022Date of Patent: July 23, 2024Assignee: SK hynix Inc.Inventors: Seung Wook Ryu, Wan Sup Shin
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Publication number: 20240178279Abstract: A semiconductor device includes a gate structure including insulating layers and conductive layers that are alternately stacked, a channel layer located in the gate structure, a silicide layer located in the channel layer, and a memory layer surrounding the channel layer. At least one of the channel layer, the silicide layer, and the memory layer includes a halogen element.Type: ApplicationFiled: April 26, 2023Publication date: May 30, 2024Applicant: SK hynix Inc.Inventors: Wan Sup SHIN, Yoon Ho KANG, Ji Seong KIM
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Publication number: 20240162149Abstract: A semiconductor device including: a gate structure in which conductive layers and insulating layers are alternately stacked; contact plug extending in a stacking direction of the insulating layers through the gate structure; first spacer layers each located between the conductive layer and the contact plug; and second spacer layers each located between the contact plug and the first spacer layer.Type: ApplicationFiled: May 16, 2023Publication date: May 16, 2024Applicant: SK hynix Inc.Inventors: Ji Seong KIM, Yoon Ho KANG, Wan Sup SHIN, Seok Min JEON
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Patent number: 11925021Abstract: A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.Type: GrantFiled: December 13, 2021Date of Patent: March 5, 2024Assignee: SK hynix Inc.Inventors: Young Geun Jang, Wan Sup Shin, Ki Hong Lee, Jae Jung Lee
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Publication number: 20240057319Abstract: A semiconductor device includes: a lower structure; a horizontal layer extending in a direction parallel to a surface of the lower structure over the lower structure, and including a first end and a second end; a discrete contact node coupled to the first end of the horizontal layer to extend in a direction perpendicular to the surface of the lower structure and including a first impurity; and a doped region in the horizontal layer including the first impurity which is diffused from the discrete contact node.Type: ApplicationFiled: March 17, 2023Publication date: February 15, 2024Inventors: Wan Sup SHIN, Seung Wook RYU, Kyung Bin CHUN
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Publication number: 20230255015Abstract: A semiconductor device includes: a substrate; a body recess in the substrate; a body dielectric layer over the body recess; an active layer extending in a direction parallel to the substrate over the substrate; a contact node over an end portion of the active layer and perpendicular to the substrate; and a conductive line coupled to the contact node and extended perpendicular to the substrate.Type: ApplicationFiled: July 13, 2022Publication date: August 10, 2023Inventors: Wan Sup Shin, Seung Wook Ryu, Seung Mi Yeo
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Publication number: 20230225127Abstract: A semiconductor device includes a first stack structure including first interlayer insulating layers and first conductive patterns alternately stacked on each other in a first direction and a second conductive pattern comprising electrode portions and a connecting portion. The electrode portions of the second conductive pattern are stacked to be spaced apart from each other above the first stack structure. The connecting portion of the second conductive pattern extends in the first direction to intersect the electrode portions and couples the electrode portions. The semiconductor device further includes a vertical channel and a vertical conductive structure that pass through the first stack structure and the electrode portions of the second conductive pattern. The vertical conductive structure is spaced apart from the first stack structure and the second conductive pattern.Type: ApplicationFiled: January 12, 2023Publication date: July 13, 2023Applicant: SK hynix Inc.Inventors: Young Geun JANG, Wan Sup SHIN, Ki Hong LEE, Jae Jung LEE
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Publication number: 20230107126Abstract: A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.Type: ApplicationFiled: December 6, 2022Publication date: April 6, 2023Applicant: SK hynix Inc.Inventors: Young Geun JANG, Wan Sup SHIN, Ki Hong LEE, Jae Jung LEE
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Publication number: 20230040214Abstract: A method for fabricating a vertical semiconductor device may include forming a lower-level stack including a source sacrificial layer over a semiconductor substrate; forming an upper-level stack including dielectric layers and sacrificial layers over the lower-level stack; forming a vertical channel structure including a channel layer that penetrates the upper-level stack and the lower-level stack; forming a slit that penetrates the upper-level stack while exposing the source sacrificial layer; forming a lateral recess that extends from the slit by removing the source sacrificial layer; forming a first contact layer which is coupled to a portion of the channel layer while filling the lateral recess; selectively forming a second contact layer over an exposed surface of the first contact layer; and selectively forming a chemical barrier layer over the second contact layer.Type: ApplicationFiled: February 15, 2022Publication date: February 9, 2023Inventors: Wan Sup SHIN, Jong Gi Kim, Seung Wook Ryu, Jun Seok Oh, Heung Ju Lee
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Patent number: 11552101Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalk of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.Type: GrantFiled: January 20, 2021Date of Patent: January 10, 2023Assignee: SK hynix Inc.Inventors: Wan Sup Shin, Ki Hong Lee, Jae Jung Lee, Young Geun Jang
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Patent number: 11296188Abstract: A semiconductor device includes a source structure, a bit line, a stacked structure between the source structure and the bit line, a source contact structure penetrating the stacked structure and electrically coupled to the source structure, and a protective pattern interposed between the source contact structure and the source structure and having a varying thickness depending on an area of the protective pattern.Type: GrantFiled: February 14, 2020Date of Patent: April 5, 2022Assignee: SK hynix Inc.Inventors: Hee Soo Kim, Young Ho Yang, Chang Soo Lee, Wan Sup Shin
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Publication number: 20220102376Abstract: A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Applicant: SK hynix Inc.Inventors: Young Geun JANG, Wan Sup SHIN, Ki Hong LEE, Jae Jung LEE
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Patent number: 11233063Abstract: A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.Type: GrantFiled: April 17, 2019Date of Patent: January 25, 2022Assignee: SK hynix Inc.Inventors: Young Geun Jang, Wan Sup Shin, Ki Hong Lee, Jae Jung Lee
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Publication number: 20210143177Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalk of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Applicant: SK hynix Inc.Inventors: Wan Sup SHIN, Ki Hong LEE, Jae Jung LEE, Young Geun JANG
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Patent number: 10930670Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.Type: GrantFiled: May 29, 2019Date of Patent: February 23, 2021Assignee: SK hynix Inc.Inventors: Wan Sup Shin, Ki Hong Lee, Jae Jung Lee, Young Geun Jang
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Publication number: 20210036109Abstract: A semiconductor device includes a source structure, a bit line, a stacked structure between the source structure and the bit line, a source contact structure penetrating the stacked structure and electrically coupled to the source structure, and a protective pattern interposed between the source contact structure and the source structure and having a varying thickness depending on an area of the protective pattern.Type: ApplicationFiled: February 14, 2020Publication date: February 4, 2021Applicant: SK hynix Inc.Inventors: Hee Soo KIM, Young Ho YANG, Chang Soo LEE, Wan Sup SHIN
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Publication number: 20200135755Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.Type: ApplicationFiled: May 29, 2019Publication date: April 30, 2020Applicant: SK hynix Inc.Inventors: Wan Sup SHIN, Ki Hong LEE, Jae Jung LEE, Young Geun JANG