Patents by Inventor Wanbing YI

Wanbing YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190326509
    Abstract: Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 24, 2019
    Inventors: Wanbing YI, Curtis Chun-I HSIEH, Yi JIANG, Bharat BHUSHAN, Mahesh BHATKAR, Juan Boon TAN
  • Publication number: 20190326352
    Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.
    Type: Application
    Filed: July 5, 2019
    Publication date: October 24, 2019
    Inventors: Wanbing YI, Curtis Chun-I HSIEH, Juan Boon TAN, Soh Yun SIAH, Hai CONG, Alex SEE, Young Seon YOU, Danny Pak-Chum SHUM, Hyunwoo YANG
  • Patent number: 10446607
    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDARIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
  • Publication number: 20190305041
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Pinghui LI, Haiqing ZHOU, Liying ZHANG, Wanbing YI, Ming ZHU, Danny Pak-Chum SHUM, Darin CHAN
  • Patent number: 10431732
    Abstract: Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 1, 2019
    Assignees: GLOBALFOUNDRIES SINGAPORE PTE. LTD., AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Bhushan Bharat, Shan Gao, Danny Pak-Chum Shum, Wanbing Yi, Juan Boon Tan, Wei Yi Lim, Teck Guan Lim, Michael Han Kim Kwong, Eva Wai Leong Ching
  • Publication number: 20190288201
    Abstract: Methods of forming planar RRAM and vertical RRAM with tip electrodes and the resulting devices are provided. Embodiments include forming a first metal oxide layer on a first dielectric layer; forming and patterning a mask layer over the first metal oxide layer; etching the first metal oxide through the mask layer to form openings for a first and second metal electrodes; removing the mask layer; forming the first and second metal electrodes in the openings; and forming a second metal oxide layer over the first and second metal electrodes, wherein the first and second metal electrodes are v-shaped in top view with tips of the first and second metal electrodes facing each other and a portion of the second metal oxide layer being formed between the tips of the first and second electrodes.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Inventors: Jianxun SUN, Juan Boon TAN, Kwang Sing YEW, Wanbing YI, Curtis Chun-I HSIEH, Tupei CHEN
  • Publication number: 20190287921
    Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Bharat BHUSHAN, Juan Boon TAN, Boo Yang JUNG, Wanbing YI, Danny Pak-Chum SHUM
  • Patent number: 10374005
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu, Danny Pak-Chum Shum, Darin Chan
  • Publication number: 20190229261
    Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Inventors: Curtis Chun-I HSIEH, Lup San LEONG, Wanbing YI, Cing Gie LIM, Yi JIANG, Juan Boon TAN
  • Publication number: 20190229068
    Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Inventors: Bharat BHUSHAN, Juan Boon TAN, Boo Yang JUNG, Wanbing YI, Danny Pak-Chum SHUM
  • Patent number: 10361162
    Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Boo Yang Jung, Wanbing Yi, Danny Pak-Chum Shum
  • Publication number: 20190214550
    Abstract: Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Bharat BHUSHAN, Juan Boon TAN, Danny Pak-Chum SHUM, Wanbing YI
  • Patent number: 10347826
    Abstract: Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Danny Pak-Chum Shum, Wanbing Yi
  • Publication number: 20190206928
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAIVI layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Pinghui LI, Haiqing ZHOU, Liying ZHANG, Wanbing YI, Ming ZHU, Danny Pak-Chum SHUM, Darin CHAN
  • Publication number: 20190198343
    Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Inventors: Curtis Chun-I HSIEH, Wanbing YI, Yi JIANG, Juan Boon TAN, Zhehui WANG
  • Publication number: 20190115223
    Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 18, 2019
    Inventors: Curtis Chun-I HSIEH, Wanbing YI, Yi JIANG, Juan Boon TAN, Zhehui WANG
  • Patent number: 10262868
    Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wanbing Yi, Yi Jiang, Juan Boon Tan, Zhehui Wang
  • Patent number: 10256273
    Abstract: High density resistive memory structures, integrate circuits with high density resistive memory structures, and methods for fabricating high density resistive memory structures are provided. In an embodiment, a high density resistive memory structure includes a semiconductor substrate and a plurality of first electrodes in a first plane in and/or over the semiconductor substrate. Further, the high density resistive memory structure includes a plurality of second electrodes in a second plane in and/or over the semiconductor substrate. The second plane is parallel to the first plane, and each second electrode in the plurality of second electrodes crosses over or under each first electrode in the plurality of first electrodes at a series of cross points. Each second electrode in the plurality of second electrodes is non-linear and the series of cross points formed by each respective second electrode is non-linear.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 9, 2019
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Curtis Chun-I Hsieh, Juan Boon Tan, Wanbing Yi, Yi Jiang
  • Publication number: 20190074434
    Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.
    Type: Application
    Filed: October 30, 2018
    Publication date: March 7, 2019
    Inventors: Wanbing YI, Neha NAYYAR, Curtis Chun-I HSIEH, Mahesh BHATKAR, Wenjun LIU, Juan Boon TAN
  • Patent number: 10217794
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Juan Boon Tan, Mahesh Bhatkar, Bhushan Bharat, Wanbing Yi