Patents by Inventor Wanbing YI

Wanbing YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9793208
    Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Haifeng Sheng, Juan Boon Tan, Wanbing Yi, Daxiang Wang, Soh Yun Siah
  • Patent number: 9793185
    Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Daxiang Wang, Juan Boon Tan, Kemao Lin, Shaoqiang Zhang
  • Patent number: 9786839
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetoresistive random access memory (MRAM) chip magnetic shielding and vertical stacking capabilities processed at the wafer-level are disclosed. The method includes providing a magnetic shield in the through silicon vias and/or through silicon trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the MRAM region and also at the front side and back side of the chip. Magnetic shield in the through silicon trenches connects front side and back side magnetic shield. Magnetic shield in the through silicon vias provides vertical stacking, magnetic shielding and electrical connection of the MRAM chips to form 3D IC packages. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the MRAM region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: October 10, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Wanbing Yi, Pak-Chum Danny Shum
  • Patent number: 9728474
    Abstract: A semiconductor chip includes an active area including a plurality of integrated circuit structures, a seal ring enclosing the active area, a corner area of the semiconductor chip that is outside of the seal ring, and an electronic test structure disposed within the corner area. Semiconductor wafers including the above-noted semiconductor chips, as well as methods for fabricating semiconductor wafers including the above-noted semiconductor chips, are also disclosed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 8, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Juan Boon Tan, Mahesh Bhatkar, Danny Pak-Chum Shum
  • Publication number: 20170194229
    Abstract: A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Wanbing Yi, Mahesh Bhatkar, Chin Chuan Neo, Juan Boon Tan
  • Patent number: 9698200
    Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Ming Zhu, Shunqiang Gong, Wanbing Yi, Darin Chan, Yiang Aun Nga
  • Publication number: 20170162501
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with interlevel dielectric (ILD) layers having interconnect levels. Each of the ILD layers has a metal level dielectric which includes one or more metal lines and a via level dielectric which includes one or more via contacts. A crack stop layer is formed within one of the via level dielectric of one of the ILD layers. The crack stop layer prevents crack formation in the ILD layer or crack propagation to underlying ILD layer.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 8, 2017
    Inventors: Wanbing YI, Cuiling ZHOU, Juan Boon TAN
  • Publication number: 20170125396
    Abstract: A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.
    Type: Application
    Filed: January 9, 2017
    Publication date: May 4, 2017
    Inventors: Wei SHAO, Juan Boon TAN, Wei LIU, Wanbing YI
  • Publication number: 20170104029
    Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.
    Type: Application
    Filed: October 7, 2016
    Publication date: April 13, 2017
    Inventors: Pinghui LI, Ming ZHU, Shunqiang GONG, Wanbing YI, Darin CHAN, Yiang Aun NGA
  • Patent number: 9613897
    Abstract: Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Mahesh Bhatkar, Lulu Peng, Wanbing Yi, Juan Boon Tan, Luke England
  • Publication number: 20170092584
    Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Haifeng SHENG, Juan Boon TAN, Wanbing YI, Daxiang WANG, Soh Yun SIAH
  • Publication number: 20170092693
    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions and providing a plurality of interlevel dielectric (ILD) levels having tight pitch over the first and second regions of the substrate. An ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds to Mx, an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes via level Vx and metal level Mx+1 and the next overlying ILD level corresponds to a third ILD level includes via level Vx+1 and metal level Mx+2. The method includes forming a two-terminal device element is formed in between metal level Mx and via level Vx+1 in the first region.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 30, 2017
    Inventors: Juan Boon TAN, Wanbing YI, Yi JIANG, Curtis Chun-I HSIEH, Danny Pak-Chum SHUM
  • Publication number: 20170025601
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetoresistive random access memory (MRAM) chip magnetic shielding and vertical stacking capabilities processed at the wafer-level are disclosed. The method includes providing a magnetic shield in the through silicon vias and/or through silicon trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the MRAM region and also at the front side and back side of the chip. Magnetic shield in the through silicon trenches connects front side and back side magnetic shield. Magnetic shield in the through silicon vias provides vertical stacking, magnetic shielding and electrical connection of the MRAM chips to form 3D IC packages. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the MRAM region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.
    Type: Application
    Filed: September 7, 2016
    Publication date: January 26, 2017
    Inventors: Bharat BHUSHAN, Juan Boon TAN, Wanbing YI, Pak-Chum Danny SHUM
  • Publication number: 20170025471
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed. The method includes providing a magnetic shield at the front side of the chip, back side of the chip, and also in the deep trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the prime die region. Magnetic shield in the deep trenches connects front side and back side magnetic shield. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the prime die region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.
    Type: Application
    Filed: March 24, 2016
    Publication date: January 26, 2017
    Inventors: Bharat BHUSHAN, Juan Boon TAN, Wanbing YI, Danny Pak-Chum SHUM, Shan GAO, Kangho LEE
  • Patent number: 9553129
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with a memory cell region. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer includes a first upper interconnect level with one or more metal lines in the memory cell region. A second upper dielectric layer is provided over the first upper dielectric layer. The second upper dielectric layer includes a via plug coupled to the metal line of the first upper interconnect level. An alignment trench which extends from a top surface of the second upper dielectric layer to a portion of the second upper dielectric layer is formed. Various layers of a MTJ stack are formed over the second upper dielectric layer. Profile of the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which serves as an alignment mark.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yi Jiang, Wanbing Yi, Juan Boon Tan, Danny Pak-Chum Shum
  • Patent number: 9543192
    Abstract: A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wei Shao, Juan Boon Tan, Wei Liu, Wanbing Yi
  • Patent number: 9520371
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 13, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Wanbing Yi, Wei Lu, Alex See, Juan Boon Tan
  • Patent number: 9520299
    Abstract: A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 13, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Chin Chuan Neo, Hai Cong, Kin Wai Tang, Weining Li, Juan Boon Tan
  • Publication number: 20160359100
    Abstract: Magnetic random access memory (MRAM) fan-out wafer level packages with package level and chip level magnetic shielding and methods of forming these magnetic shields processed at the wafer-level are disclosed. The method includes providing a MRAM wafer prepared with a plurality of MRAM dies. The MRAM wafer is processed to form a magnetic shield layer over the front side of the MRAM wafer, and the wafer is separated into a plurality of individual dies. An individual MRAM die includes front, back and lateral surfaces and the magnetic shield layer is disposed over the front surface of the MRAM die. Magnetic shield structures are provided over the individual MRAM dies. The magnetic shield structure encapsulates and surrounds back and lateral surfaces of the MRAM die. An encapsulation layer is formed to cover the individual MRAM dies which are provided with magnetic shield structures.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Bharat BHUSHAN, Juan Boon TAN, Wanbing YI, Pak-Chum Danny SHUM
  • Publication number: 20160351792
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the device-level are disclosed. The method includes providing a magnetic shield structure that is substantially surrounding a magnetic tunnel junction (MTJ) bit or device of a MTJ array within the MRAM region. The magnetic shield may be configured in the form of a cylindrical shield structure or magnetic shield spacer that substantially surrounds the MTJ bit or device. The magnetic shield structure in the form of cylindrical shield structure or magnetic shield spacer may include top and/or bottom plate shield. The magnetic shield structure in various forms and configurations protect the MTJ stack from external or local magnetic fields.
    Type: Application
    Filed: May 23, 2016
    Publication date: December 1, 2016
    Inventors: Yi JIANG, Bharat BHUSHAN, Wanbing YI, Juan Boon TAN, Pak-Chum Danny SHUM