Patents by Inventor Wanbing YI

Wanbing YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150177319
    Abstract: Integrated circuits with copper hillock-detecting structures and methods for detecting copper hillocks using the same are disclosed. In an exemplary embodiment, an integrated circuit includes a copper hillock-detecting structure. The copper hillock-detecting structure includes a copper metallization layer and an intermediate plate structure adjacent to the copper metallization layer. The intermediate plate structure includes a conducting material plate. The intermediate plate structure further includes a plurality of vias electrically and physically connected with the conducting material plate. The copper hillock-detecting structure further includes a sensing plate adjacent to the intermediate plate and electrically and physically connected with the plurality of vias.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wanbing YI, Juan Boon Tan, Wei Shao, Gong Shun Qiang
  • Publication number: 20150069561
    Abstract: A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 12, 2015
    Inventors: Juan Boon TAN, Wanbing YI, Danny Pak-Chum SHUM, Yi JIANG
  • Publication number: 20150061156
    Abstract: A bonding pad and a method of manufacturing a bonding pad are presented. The method includes providing a substrate prepared with circuits component and an interlevel dielectric (ILD) layer with interconnects. A final passivation level is formed on the substrate surface and includes a pad opening. A wire bond in contact with the pad interconnect is formed in the pad opening. The pad interconnect is suitable for, for example, copper wire bond and can avoid the formation of intermetallic compound during wire bonding. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 5, 2015
    Inventors: Yi JIANG, Xiaohua ZHAN, Wanbing YI, Mahesh BHATKAR, Yoke Leng LIM, Siow Lee CHWA, Juan Boon TAN, Soh Yun SIAH
  • Publication number: 20140264235
    Abstract: Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.
    Type: Application
    Filed: May 30, 2013
    Publication date: September 18, 2014
    Inventors: Shunqiang GONG, Juan Boon TAN, Lei WANG, Wei LIU, Wanbing YI, Jens OSWALD