Patents by Inventor Wang-Chin Chen

Wang-Chin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490502
    Abstract: A power distribution network adapted to provide power to a plurality of components in an integrated circuit is provided. The power distribution network includes a power distribution trunk path, a plurality of first power distribution branch paths, and a plurality of second power distribution branch paths. The power distribution trunk path is used for transmitting the power. A long axis direction of the power distribution trunk path is a first direction. The first power distribution branch paths and the second power distribution branch paths are electrically connected to the power distribution trunk path. A long axis direction of the first power distribution branch paths is a second direction different from the first direction. A long axis direction of the second power distribution branch paths is a third direction different from the first direction and the second direction.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: November 26, 2019
    Assignee: Faraday Technology Corp.
    Inventors: Yi-Yeh Yang, Wang-Chin Chen, Po-Chen Lo, Shang-Ru Lin, Jen-Hsing Lin, Jin-Cheng Chen
  • Publication number: 20190122986
    Abstract: A power distribution network adapted to provide power to a plurality of components in an integrated circuit is provided. The power distribution network includes a power distribution trunk path, a plurality of first power distribution branch paths, and a plurality of second power distribution branch paths. The power distribution trunk path is used for transmitting the power. A long axis direction of the power distribution trunk path is a first direction. The first power distribution branch paths and the second power distribution branch paths are electrically connected to the power distribution trunk path. A long axis direction of the first power distribution branch paths is a second direction different from the first direction. A long axis direction of the second power distribution branch paths is a third direction different from the first direction and the second direction.
    Type: Application
    Filed: January 3, 2018
    Publication date: April 25, 2019
    Applicant: Faraday Technology Corp.
    Inventors: Yi-Yeh Yang, Wang-Chin Chen, Po-Chen Lo, Shang-Ru Lin, Jen-Hsing Lin, Jin-Cheng Chen
  • Publication number: 20160285256
    Abstract: An integrated circuit (IC) including a unit area, a first input/output (IO) cell, a second IO cell, an electrostatic discharge (ESD) component, a first IO pad and a second IO pad is provided. The unit area is divided into several subareas, wherein a subarea of an ith column and a jth row of those subareas is defined as SA(i,j). The first IO cell is arranged in subareas SA(i,j) and SA(i,j+1) of those subareas. The second IO cell is arranged in a subarea SA(i+1,j+1) of those subareas. The ESD component is arranged in at lease one of the subareas of the jth row. The first IO pad is arranged on the first IO cell, and electrically connected to the first IO cell. The second IO pad is arranged on the second IO cell, and electrically connected to the second IO cell.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 29, 2016
    Applicant: Faraday Technology Corp.
    Inventors: Jeng-Huang Wu, Tang-Long Chang, Wang-Chin Chen
  • Patent number: 7900107
    Abstract: The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 1, 2011
    Assignee: Faraday Technology Corp.
    Inventors: Wang-Chin Chen, Augusli Kifli
  • Patent number: 7888970
    Abstract: A switch controlling circuit, which comprises: a frequency programmable clock signal generator and a plurality of registers. The frequency programmable clock signal generator serves to generate a frequency controllable clock signal. The registers comprises: a first stage register, for receiving an input signal and the frequency controllable clock signal, and for outputting a first output signal, which is utilized to control a first switch device, according to the input signal and the frequency controllable clock signal; and a second stage register, for receiving the first output signal and the frequency controllable clock signal, and for outputting a second output signal, which is utilized to control a second switch device, according to the first output signal and the frequency controllable clock signal.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: February 15, 2011
    Assignee: Faraday Technology Corp.
    Inventor: Wang-Chin Chen
  • Publication number: 20110025401
    Abstract: A switch controlling circuit, which comprises: a frequency programmable clock signal generator and a plurality of registers. The frequency programmable clock signal generator serves to generate a frequency controllable clock signal. The registers comprises: a first stage register, for receiving an input signal and the frequency controllable clock signal, and for outputting a first output signal, which is utilized to control a first switch device, according to the input signal and the frequency controllable clock signal; and a second stage register, for receiving the first output signal and the frequency controllable clock signal, and for outputting a second output signal, which is utilized to control a second switch device, according to the first output signal and the frequency controllable clock signal.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 3, 2011
    Inventor: Wang-Chin Chen
  • Patent number: 7821281
    Abstract: Method and apparatus of testing die to die interconnection for system in package (SiP). For testing a die to die interconnection connected between two pads of two dice, an IO buffer, e.g., a bi-directional IO buffer, in one of the two dice coupled to one of the two pads is arranged. An oscillating feedback is formed between an output port and an input port of the IO buffer, such that a state, e.g., an open state, a short state or a normal state of the die to die interconnection is tested according to a timing characteristic, e.g., a frequency, of a signal of the IO buffer.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: October 26, 2010
    Assignee: Faraday Technology Corp.
    Inventor: Wang Chin Chen
  • Publication number: 20100213965
    Abstract: Method and apparatus of testing die to die interconnection for system in package (SiP). For testing a die to die interconnection connected between two pads of two dice, an IO buffer, e.g., a bi-directional IO buffer, in one of the two dice coupled to one of the two pads is arranged. An oscillating feedback is formed between an output port and an input port of the IO buffer, such that a state, e.g., an open state, a short state or a normal state of the die to die interconnection is tested according to a timing characteristic, e.g., a frequency, of a signal of the IO buffer.
    Type: Application
    Filed: February 23, 2009
    Publication date: August 26, 2010
    Applicant: FARADAY TECHNOLOGY CORPORATION
    Inventor: WANG CHIN CHEN
  • Patent number: 7675308
    Abstract: For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; and a voltage level at the decoupling capacitance is analyzed or a leakage current flowing the power switch is measured. So that, whether the power switch is passed or failed is identified.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 9, 2010
    Assignee: Faraday Technology Corp.
    Inventors: Wang-Chin Chen, Chun-Sung Su
  • Publication number: 20100045327
    Abstract: For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; and a voltage level at the decoupling capacitance is analyzed or a leakage current flowing the power switch is measured. So that, whether the power switch is passed or failed is identified.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Wang-Chin Chen, Chun-Sung Su
  • Publication number: 20100050030
    Abstract: The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Wang-Chin Chen, Augusli Kifli
  • Patent number: 7187163
    Abstract: A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 6, 2007
    Assignee: Faraday Technology Corp.
    Inventors: Shyh-An Chi, Wang-Chin Chen
  • Publication number: 20060158178
    Abstract: A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.
    Type: Application
    Filed: January 19, 2005
    Publication date: July 20, 2006
    Inventors: Shyh-An Chi, Wang-Chin Chen