Abstract: The embodiments described herein facilitate performing bipolar switching of a confined phase change memory (PCM) with a metallic liner, wherein the phase change memory and the metallic liner are located between a first electrode and a second electrode of a semiconductor structure, wherein a first voltage is applied to the first electrode while the second electrode is grounded, and wherein a second voltage is applied to the second electrode while the first electrode is grounded. The bipolar switching can be performed so as to produce a plurality of resistance states. Thus, this confined PCM can be utilized as a multi-level cell (MLC) memory.

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.

Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.

Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.

Abstract: A memory access device that includes a first terminal with a first terminal workfunction and a chalcogenide-based selector layer with a first surface and a second surface opposite the first surface. A first control metal layer is positioned in physical and electrical contact with the first terminal and the first surface of the chalcogenide-based selector layer. The first control metal layer includes a first control workfunction different than the first terminal workfunction. A second terminal with a second terminal workfunction is positioned proximate the second surface of the chalcogenide-based selector layer.

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Abstract: A plurality of memory cells in a 3D cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

Abstract: A plurality of memory cells in a 3D cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.

Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.

Abstract: A plurality of memory cells in a cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.

Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction.

Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction.