Patents by Inventor Wanqing Cao
Wanqing Cao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967707Abstract: Methods for producing nanostructures from copper-based catalysts on porous substrates, particularly silicon nanowires on carbon-based substrates for use as battery active materials, are provided. Related compositions are also described. In addition, novel methods for production of copper-based catalyst particles are provided. Methods for producing nanostructures from catalyst particles that comprise a gold shell and a core that does not include gold are also provided.Type: GrantFiled: February 18, 2023Date of Patent: April 23, 2024Assignee: OneD Material, Inc.Inventors: Wanqing Cao, Virginia Robbins, Yimin Zhu
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Publication number: 20230411602Abstract: Methods for producing nanostructures from copper-based catalysts on porous substrates, particularly silicon nanowires on carbon-based substrates for use as battery active materials, are provided. Related compositions are also described. In addition, novel methods for production of copper-based catalyst particles are provided. Methods for producing nanostructures from catalyst particles that comprise a gold shell and a core that does not include gold are also provided.Type: ApplicationFiled: February 18, 2023Publication date: December 21, 2023Applicant: OneD Material, Inc.Inventors: Wanqing CAO, Virginia ROBBINS, Yimin ZHU
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Patent number: 11616225Abstract: Methods for producing nanostructures from copper-based catalysts on porous substrates, particularly silicon nanowires on carbon-based substrates for use as battery active materials, are provided. Related compositions are also described. In addition, novel methods for production of copper-based catalyst particles are provided. Methods for producing nanostructures from catalyst particles that comprise a gold shell and a core that does not include gold are also provided.Type: GrantFiled: March 15, 2019Date of Patent: March 28, 2023Assignee: ONED MATERIAL, INC.Inventors: Wanqing Cao, Virginia Robbins, Yimin Zhu
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Publication number: 20190214641Abstract: Methods for producing nanostructures from copper-based catalysts on porous substrates, particularly silicon nanowires on carbon-based substrates for use as battery active materials, are provided. Related compositions are also described. In addition, novel methods for production of copper-based catalyst particles are provided. Methods for producing nanostructures from catalyst particles that comprise a gold shell and a core that does not include gold are also provided.Type: ApplicationFiled: March 15, 2019Publication date: July 11, 2019Inventors: Wanqing Cao, Virginia Robbins, Yimin Zhu
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Patent number: 10243207Abstract: Methods for producing nanostructures from copper-based catalysts on porous substrates, particularly silicon nanowires on carbon-based substrates for use as battery active materials, are provided. Related compositions are also described. In addition, novel methods for production of copper-based catalyst particles are provided. Methods for producing nanostructures from catalyst particles that comprise a gold shell and a core that does not include gold are also provided.Type: GrantFiled: July 24, 2012Date of Patent: March 26, 2019Assignee: OneD Material LLCInventors: Wanqing Cao, Virginia Robbins, Yimin Zhu
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Publication number: 20160356898Abstract: A scintillator device includes a scintillator layer on a substrate and a foil layer that covers the scintillator layer. The foil layer overlaps an outer edge of the scintillator layer and is adhered to a portion of the substrate surrounding the scintillator layer to form at least part of a first moisture barrier between the scintillator layer and the surrounding environment. A sealant overlaps an outer edge of the foil layer onto a portion of the substrate surrounding the foil layer to form at least part of a second moisture barrier between the scintillator layer and the surrounding environment.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventor: Wanqing CAO
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Patent number: 9513383Abstract: A scintillator device includes a scintillator layer on a substrate and a foil layer that covers the scintillator layer. The foil layer overlaps an outer edge of the scintillator layer and is adhered to a portion of the substrate surrounding the scintillator layer to form at least part of a first moisture barrier between the scintillator layer and the surrounding environment. A sealant overlaps an outer edge of the foil layer onto a portion of the substrate surrounding the foil layer to form at least part of a second moisture barrier between the scintillator layer and the surrounding environment.Type: GrantFiled: June 3, 2015Date of Patent: December 6, 2016Assignee: PerkinElmer Holdings, Inc.Inventor: Wanqing Cao
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Publication number: 20150086871Abstract: Methods for producing nanostructures from copper-based catalysts on porous substrates, particularly silicon nanowires on carbon-based substrates for use as battery active materials, are provided. Related compositions are also described. In addition, novel methods for production of copper-based catalyst particles are provided. Methods for producing nanostructures from catalyst particles that comprise a gold shell and a core that does not include gold are also provided.Type: ApplicationFiled: July 24, 2012Publication date: March 26, 2015Applicant: ONED MATERIAL LLCInventors: Wanqing Cao, Virginia Robbins
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Patent number: 7400026Abstract: The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.Type: GrantFiled: January 26, 2006Date of Patent: July 15, 2008Assignee: Integrated Device Technology, Inc.Inventors: Gaolong Jin, Wanqing Cao, Guo-Qiang Lo, Shih-Ked Lee
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Patent number: 7214990Abstract: The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.Type: GrantFiled: February 22, 2005Date of Patent: May 8, 2007Assignee: Integrated Device Technology, Inc.Inventors: Shih-Ked Lee, Chuen-Der Lien, Louis Huang, Gaolong Jin, Wanqing Cao, Guo-Qiang Lo
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Patent number: 7078306Abstract: The present invention relates to a method for forming a thin film resistor and a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a portion of the gate structure. A layer of titanium nitride is deposited using a chemical vapor deposition process. A rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure. A metal layer is deposited and patterned to form an interconnect structure that electrically couples the titanium oxynitride structure to other circuitry.Type: GrantFiled: March 22, 2004Date of Patent: July 18, 2006Assignee: Integrated Device Technology, Inc.Inventors: Gaolong Jin, Wanqing Cao, Guo-Qiang Lo, Shih-Ked Lee
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Publication number: 20060118910Abstract: The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited A and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.Type: ApplicationFiled: January 26, 2006Publication date: June 8, 2006Inventors: Gaolong Jin, Wanqing Cao, Guo-Qiang Lo, Shih-Ked Lee
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Patent number: 6872668Abstract: An improved method is provided for etching back a tungsten layer that overlies a titanium nitride adhesion layer on a semiconductor structure. This method includes the steps of: (1) performing a first plasma etchback of the tungsten layer for a first predetermined time period, such that a thin layer of tungsten remains over the adhesion layer at the end of the first plasma etchback, (2) actively or passively cooling the resulting semiconductor structure to a temperature of 35° C. or lower, and then (3) performing a second plasma etchback of the tungsten layer until an endpoint is detected, thereby exposing the adhesion layer. Cooling the semiconductor structure prior to the second plasma etchback ensures that the titanium nitride adhesion layer is at a relatively low temperature during the second plasma etchback. The titanium nitride adhesion layer etches significantly slower at lower temperatures, thereby making it easier to stop the second plasma etchback on the adhesion layer.Type: GrantFiled: September 26, 2000Date of Patent: March 29, 2005Assignee: Integrated Device Technology, Inc.Inventors: Wanqing Cao, Guo-Qiang Lo, Shih-Ked Lee, Hongyong Xue
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Patent number: 6765269Abstract: A semiconductor structure is provided that includes a gate, a dielectric spacer located adjacent to a sidewall of the gate, a source/drain region, and a continuous silicide strap located over the gate, the dielectric spacer and the source/drain region. The silicide strap provides an electrical connection between the gate and the source drain region. In one embodiment, the silicide strap is formed by a method that includes the steps of (1) implanting a semiconductor material, such as silicon, into upper surfaces of the gate, the dielectric spacer, and the source/drain region, (2) depositing a refractory metal over the implanted semiconductor material, and (3) reacting the refractory metal with the implanted semiconductor material, thereby forming the continuous silicide strap at the upper surfaces of the gate, the dielectric spacer and the source/drain region. Advantageously, the dielectric spacer does not need to be removed prior to forming the silicide strap.Type: GrantFiled: January 26, 2001Date of Patent: July 20, 2004Assignee: Integrated Device Technology, Inc.Inventors: Eric Lee, Dave Cobert, Wanqing Cao
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Patent number: 6627543Abstract: Disclosed are methods and systems for forming salicide, in which a semiconductor substrate is provided with at least one exposed silicon surface. The semiconductor substrate is placed into a sputtering chamber. A silicide-forming metal layer, formed of a metal such as Co, Ni, is sputter-deposited over the exposed silicon surface. A process temperature is controlled below room temperature during the sputter deposition and preferably between approximately 0° C. to 10° C. The silicide-forming metal layer formed on the exposed silicon surface is first annealed to convert the silicide-forming metal layer into a salicide layer. Also, the system of the present invention is comprised of a sputter chamber including a mount for mounting a semiconductor substrate and a cooling mechanism coupled with the mount for cooling the semiconductor substrate. The cooling mechanism includes a controller to maintain a process temperature below room temperature.Type: GrantFiled: May 3, 2000Date of Patent: September 30, 2003Assignee: Integrated Device Technology, Inc.Inventors: Wanqing Cao, Guo-Qiang Patrick Lo, Shih-Ked Lee, Robert B. Hixson, Eric S. Lee
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Publication number: 20020102845Abstract: A semiconductor structure is provided that includes a gate, a dielectric spacer located adjacent to a sidewall of the gate, a source/drain region, and a continuous silicide strap located over the gate, the dielectric spacer and the source/drain region. The silicide strap provides an electrical connection between the gate and the source drain region. In one embodiment, the silicide strap is formed by a method that includes the steps of (1) implanting a semiconductor material, such as silicon, into upper surfaces of the gate, the dielectric spacer, and the source/drain region, (2) depositing a refractory metal over the implanted semiconductor material, and (3) reacting the refractory metal with the implanted semiconductor material, thereby forming the continuous silicide strap at the upper surfaces of the gate, the dielectric spacer and the source/drain region. Advantageously, the dielectric spacer does not need to be removed prior to forming the silicide strap.Type: ApplicationFiled: January 26, 2001Publication date: August 1, 2002Inventors: Eric Lee, Dave Cobert, Wanqing Cao
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Patent number: 6281102Abstract: An improved method is provided for fabricating a cobalt silicide structure that includes the steps of: (1) forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure, (2) loading the silicon structure into a chamber, (3) introducing a vacuum to the chamber, (4) depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide, (5) depositing a cobalt layer over the titanium layer, (6) depositing an oxygen impervious cap layer over the cobalt layer; and then (7) breaking the vacuum in the chamber, and (8) subjecting the silicon structure, the titanium layer, the cobalt layer and the cap layer to an anneal, thereby forming the cobalt silicide structure. The cap layer can be, for example, titanium or titanium nitride. The resulting cobalt silicide structure is substantially free from oxygen (i.e., oxide).Type: GrantFiled: January 13, 2000Date of Patent: August 28, 2001Assignee: Integrated Device Technology, Inc.Inventors: Wanqing Cao, Sang-Yun Lee, Guo-Qiang Lo, Shih-Ked Lee
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Patent number: 5879744Abstract: Disclosed herewith is a process of forming an aerogel composite which comprises introducing a gaseous material into a formed aerogel monolith or powder, and causing decomposition of said gaseous material in said aerogel in amounts sufficient to cause deposition of the decomposition products of the gas on the surfaces of the pores of the said aerogel.Type: GrantFiled: August 8, 1997Date of Patent: March 9, 1999Assignee: The Regents of the University of CaliforniaInventors: Wanqing Cao, Arlon Jason Hunt
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Patent number: 5864923Abstract: A method for providing aerogels, and aerogels produced according to the method, is described. As one aspect, antiperspirant compounds that are in aerogel form, and antiperspirant and deodorant compositions including such salts, are described. The method involves contacting a solution containing material to be processed with a species selected to precipitate the material and selected so as to be miscible with the solvent system of the solution. After the material is precipitated, the material may be washed with the precipitating species until it is substantially free of solvent system. Then, the precipitating species containing the material precipitate is taken above its critical point, and the supercritical fluid is exhausted above its critical temperature. Alternately, a separate isolating species is introduced to displace the precipitating species, or the precipitating species/solvent system mixture. The isolating species then is taken above its critical point, and exhausted above its critical temperature.Type: GrantFiled: August 26, 1997Date of Patent: February 2, 1999Assignees: CF Technologies, Inc., The Gillette CompanyInventors: Stephane Fabrice Rouanet, William Edward McGovern, Wanqing Cao, John M. Moses, Angel L. Carrillo, Irving M. Klotz
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Patent number: 5855953Abstract: Disclosed herewith is a process of forming an aerogel composite which comprises introducing a gaseous material into a formed aerogel monolith or powder, and causing decomposition of said gaseous material in said aerogel in amounts sufficient to cause deposition of the decomposition products of the gas on the surfaces of the pores of the said aerogel.Also disclosed are the composites made by the process.Type: GrantFiled: March 31, 1994Date of Patent: January 5, 1999Assignee: The Regents, University of CaliforniaInventors: Wanqing Cao, Arlon Jason Hunt