Patents by Inventor Warren J. Gross

Warren J. Gross has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180100778
    Abstract: A method and structure which provide an ambient pressure measurement that is unaffected by wind and localized environmental conditions. A draft range pressure transmitter is enclosed inside an enclosure which is resistant to wind and other transient localize environmental conditions. A vent cap allows slow air movement through a wall of the enclosure and forms a still air chamber for the transmitter. The pressure inside the enclosure changes at the same rate as the barometric pressure but is unaffected by wind or wind gusts.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 12, 2018
    Inventors: Warren J. Gross, Eduardo G. Miranda
  • Patent number: 9100153
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: August 4, 2015
    Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Patent number: 8108758
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: January 31, 2012
    Assignee: McGill University
    Inventors: Warren J. Gross, Shie Mannor
  • Patent number: 8108760
    Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: January 31, 2012
    Assignee: The Royal Institute for the Advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Gabi Sarkis
  • Patent number: 8095860
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: January 10, 2012
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Publication number: 20110293045
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 1, 2011
    Applicant: The Royal Institution for the advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Publication number: 20100017676
    Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 21, 2010
    Applicant: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. GROSS, Shie MANNOR, Gabi SARKIS
  • Publication number: 20090100313
    Abstract: Disclosed is a pipelined iterative process and system. Data is received at an input port and is processed in a symbolwise fashion. Processing of each symbol is performed other than relying on completing the processing of an immediately preceding symbol such that operation of the system or process is independent of an order of the input symbols.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 16, 2009
    Applicant: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. GROSS, Shie MANNOR, Saeed SHARIFI TEHRANI
  • Publication number: 20080294970
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Applicant: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Publication number: 20080256343
    Abstract: A method and system for determining convergence of iterative processes and estimating a scaling factor in decoding processes based on switching activity of the logic circuitry are provided. During execution of an iterative process using logic circuitry comprising logic gates switching activity of a plurality of the logic gates is sensed to determine switching data indicative of a total switching activity of the plurality of the logic gates. The iterative process is iterated using the logic circuitry until convergence is indicated by the switching data. Similarly, a scaling factor for use in decoding processes is determined based on the switching data.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 16, 2008
    Applicant: The Royal Institution for the advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor