Patents by Inventor Warren J. Gross
Warren J. Gross has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940295Abstract: A universal mounting system for insulated instruments includes a mounting plate which engages openings in mating parts of a self-supporting insulated enclosure. The plate supports the instrument and the enclosure independently and allows all connections to the interior of the enclosure to be made through the plate. The plate is bent to an L-shape, with one leg supported by a support structure and the other leg supporting the instrument and enclosure. A termination of a traced tubing system is housed in an enclosure mounted to an opposite side of the mounting plate. The mounting plate includes a collar, cutouts in mating sections of the enclosure fitting over the collar to mount the enclosure to the mounting plate. Illustratively, the mounting plate includes a mount plate portion connected to a supporting structure, and an instrument plate mounted to the instrument.Type: GrantFiled: February 11, 2022Date of Patent: March 26, 2024Assignee: Obcorp, LLCInventors: Marcus C. McCarter, Warren J. Gross
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Patent number: 11381260Abstract: There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.Type: GrantFiled: May 26, 2021Date of Patent: July 5, 2022Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING / MCGILL UNIVERSITYInventors: Warren J. Gross, Syed Mohsin Abbas, Thibaud Tonnellier
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Publication number: 20220163357Abstract: A universal mounting system for insulated instruments includes a mounting plate which engages openings in mating parts of a self-supporting insulated enclosure. The plate supports the instrument and the enclosure independently and allows all connections to the interior of the enclosure to be made through the plate. The plate is bent to an L-shape, with one leg supported by a support structure and the other leg supporting the instrument and enclosure. A termination of a traced tubing system is housed in an enclosure mounted to an opposite side of the mounting plate. The mounting plate includes a collar, cutouts in mating sections of the enclosure fitting over the collar to mount the enclosure to the mounting plate. Illustratively, the mounting plate includes a mount plate portion connected to a supporting structure, and an instrument plate mounted to the instrument.Type: ApplicationFiled: February 11, 2022Publication date: May 26, 2022Inventors: Marcus C. McCarter, Warren J. Gross
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Patent number: 11248938Abstract: A universal mounting system for insulated instruments includes a mounting plate which engages openings in mating parts of a self-supporting insulated enclosure. The plate supports the instrument and the enclosure independently and allows all connections to the interior of the enclosure to be made through the plate. The plate is bent to an L-shape, with one leg supported by a support structure and the other leg supporting the instrument and enclosure. A termination of a traced tubing system is housed in an enclosure mounted to an opposite side of the mounting plate. The mounting plate includes a collar, cutouts in mating sections of the enclosure fitting over the collar to mount the enclosure to the mounting plate. Illustratively, the mounting plate includes a mount plate portion connected to a supporting structure, and an instrument plate mounted to the instrument.Type: GrantFiled: June 28, 2019Date of Patent: February 15, 2022Assignee: OBCORP LLCInventors: Marcus C. McCarter, Warren J. Gross
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Publication number: 20210376953Abstract: There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.Type: ApplicationFiled: May 26, 2021Publication date: December 2, 2021Inventors: Warren J. GROSS, Syed Mohsin Abbas, Thibaud Tonnellier
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Publication number: 20210256389Abstract: There is provided a computer-implemented method of training a neural network, the neural network comprising a plurality of interconnected nodes arranged in a plurality of layers and having a plurality of weights associated therewith. The method comprises obtaining, at a computing device, a training dataset from a database, performing, at the computing device, a forward propagation on the training dataset to produce an output of the neural network, and performing, at the computing device, a backward propagation on the output of the neural network to update the plurality of weights, the backward propagation performed using an estimation of a polarity and a neutrality of gradients of the neural network.Type: ApplicationFiled: February 19, 2021Publication date: August 19, 2021Inventors: Warren J. GROSS, Amir ARDAKANI, Arash ARDAKANI
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Patent number: 10908043Abstract: A method and structure which provide an ambient pressure measurement that is unaffected by wind and localized environmental conditions. A draft range pressure transmitter is enclosed inside an enclosure which is resistant to wind and other transient localize environmental conditions. A vent cap allows slow air movement through a wall of the enclosure and forms a still air chamber for the transmitter. The pressure inside the enclosure changes at the same rate as the barometric pressure but is unaffected by wind or wind gusts.Type: GrantFiled: October 4, 2017Date of Patent: February 2, 2021Assignee: OBCORP LLCInventors: Warren J. Gross, Eduardo G. Miranda
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Publication number: 20200001951Abstract: A universal mounting system for insulated instruments includes a mounting plate which engages openings in mating parts of a self-supporting insulated enclosure. The plate supports the instrument and the enclosure independently and allows all connections to the interior of the enclosure to be made through the plate. The plate is bent to an L-shape, with one leg supported by a support structure and the other leg supporting the instrument and enclosure. A termination of a traced tubing system is housed in an enclosure mounted to an opposite side of the mounting plate. The mounting plate includes a collar, cutouts in mating sections of the enclosure fitting over the collar to mount the enclosure to the mounting plate. Illustratively, the mounting plate includes a mount plate portion connected to a supporting structure, and an instrument plate mounted to the instrument.Type: ApplicationFiled: June 28, 2019Publication date: January 2, 2020Inventors: Marcus C. McCarter, Warren J. Gross
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Publication number: 20180100778Abstract: A method and structure which provide an ambient pressure measurement that is unaffected by wind and localized environmental conditions. A draft range pressure transmitter is enclosed inside an enclosure which is resistant to wind and other transient localize environmental conditions. A vent cap allows slow air movement through a wall of the enclosure and forms a still air chamber for the transmitter. The pressure inside the enclosure changes at the same rate as the barometric pressure but is unaffected by wind or wind gusts.Type: ApplicationFiled: October 4, 2017Publication date: April 12, 2018Inventors: Warren J. Gross, Eduardo G. Miranda
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Patent number: 9100153Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.Type: GrantFiled: June 1, 2011Date of Patent: August 4, 2015Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITYInventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
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Patent number: 8108758Abstract: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.Type: GrantFiled: September 21, 2007Date of Patent: January 31, 2012Assignee: McGill UniversityInventors: Warren J. Gross, Shie Mannor
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Patent number: 8108760Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.Type: GrantFiled: July 15, 2009Date of Patent: January 31, 2012Assignee: The Royal Institute for the Advancement of Learning/McGill UniversityInventors: Warren J. Gross, Shie Mannor, Gabi Sarkis
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Patent number: 8095860Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.Type: GrantFiled: May 23, 2008Date of Patent: January 10, 2012Assignee: The Royal Institution for the Advancement of Learning/McGill UniversityInventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
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Publication number: 20110293045Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.Type: ApplicationFiled: June 1, 2011Publication date: December 1, 2011Applicant: The Royal Institution for the advancement of Learning/McGill UniversityInventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
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Publication number: 20100017676Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.Type: ApplicationFiled: July 15, 2009Publication date: January 21, 2010Applicant: The Royal Institution for the Advancement of Learning/McGill UniversityInventors: Warren J. GROSS, Shie MANNOR, Gabi SARKIS
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Publication number: 20090100313Abstract: Disclosed is a pipelined iterative process and system. Data is received at an input port and is processed in a symbolwise fashion. Processing of each symbol is performed other than relying on completing the processing of an immediately preceding symbol such that operation of the system or process is independent of an order of the input symbols.Type: ApplicationFiled: October 14, 2008Publication date: April 16, 2009Applicant: The Royal Institution for the Advancement of Learning/McGill UniversityInventors: Warren J. GROSS, Shie MANNOR, Saeed SHARIFI TEHRANI
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Publication number: 20080294970Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.Type: ApplicationFiled: May 23, 2008Publication date: November 27, 2008Applicant: The Royal Institution for the Advancement of Learning/McGill UniversityInventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
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Publication number: 20080256343Abstract: A method and system for determining convergence of iterative processes and estimating a scaling factor in decoding processes based on switching activity of the logic circuitry are provided. During execution of an iterative process using logic circuitry comprising logic gates switching activity of a plurality of the logic gates is sensed to determine switching data indicative of a total switching activity of the plurality of the logic gates. The iterative process is iterated using the logic circuitry until convergence is indicated by the switching data. Similarly, a scaling factor for use in decoding processes is determined based on the switching data.Type: ApplicationFiled: April 11, 2008Publication date: October 16, 2008Applicant: The Royal Institution for the advancement of Learning/McGill UniversityInventors: Warren J. Gross, Shie Mannor