Patents by Inventor Wataru Saito

Wataru Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10375254
    Abstract: An image forming apparatus includes a plurality of image formers each capable of forming, on a sheet, an overlap image and a non-overlap image, a fixer that fixes, on the sheet, a whole image composed of the overlap images and the non-overlap images, and a hardware processor that controls each of the plurality of image formers such that a difference in image at a boundary between the overlap image and the non-overlap image is reduced in the whole image.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: August 6, 2019
    Assignee: KONICA MINOLTA, INC.
    Inventors: Natsuko Minegishi, Wataru Watanabe, Hiroshi Morimoto, Keiki Katsumata, Kazuhiro Saito, Hiroki Shibata, Daiki Watanabe
  • Publication number: 20190190359
    Abstract: A manufacturing apparatus of an electrical rotating machine includes a coil segment shaping section for shaping a linear wire rod with a predetermined length into a coil segment with a predetermined shape consisting of a pair of slot insertion port ions extending substantially in parallel with each other and a linking portion for coupling the pair of slot insertion portions, and a coil assembling section for assembling a coil by circularly arranging the coil segments shaped in the coil segment shaping section. The coil segment shaping section and the coil assembling section are constituted to continuously perform the shaping and the assembling of the coil segment in each coil segment unit, based on control data set depending on a coil to be fabricated.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 20, 2019
    Applicant: ODAWARA ENGINEERING CO., LTD.
    Inventors: Noburo Miyawaki, Takayuki Mochizuki, Yuji Miyazaki, Wataru Wakui, Hisayoshi Watanabe, Kodai Kono, Daiki Saito, Ryo Honda, Tomohiro Ishizuka
  • Patent number: 10302681
    Abstract: According to one embodiment, a current detection circuit (12) includes: a detection resistor (Rs) provided between a solenoid valve (106) and a solenoid driver (11); an amplification unit (121) configured to amplify a detected voltage of the detection resistor (Rs); an AD converter (122) that is driven by a reference voltage (Vref) generated based on a reference current (Iref) and configured to convert an output voltage from the amplification unit (121) into a digital value and output the digital value as a detected current value (D1); and a correction unit configured to perform a correction on the detected current value (D1).
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: May 28, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masanori Otsuka, Wataru Saito, Yoshitaka Jingu, Yasuhiko Kokami, Satoshi Kondo, Junya Horishima
  • Patent number: 9905689
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; a fifth semiconductor region; an insulating portion that is provided between the second semiconductor region and the fifth semiconductor region and between the third semiconductor region and the fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; a second electrode; and a third electrode that is provided on the third semiconductor region and electrically connected to the third semiconductor region and the gate electrode.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Saito
  • Publication number: 20170368694
    Abstract: A robot hand is designed to open or close fingers using a linear actuator disposed in a housing. The robot hand has linear motion shafts extending from inside to outside the housing through guide holes formed in a wall of the housing. Each of the fingers includes a base portion and a tip portion. The base portions are secured to the linear motion shafts outside the housing. The tip portions are bent inwardly from the base portions in directions in which they approach each other and then extend toward tips of the fingers. A sealing member is disposed between each of the linear motion shafts and a corresponding one of the guide holes to hermetically isolate the inside of the housing from the outside thereof. This structure achieves an increased degree of sealing of the housing and is capable of having an increased opening or closing stroke of the fingers.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 28, 2017
    Applicant: DENSO WAVE INCORPORATED
    Inventor: Wataru SAITO
  • Publication number: 20170369833
    Abstract: A bottle includes a body, a cap mounted to a cap neck of the body. The cap has an outer peripheral portion which is provided with a protrusion. Around the cap, there is provided a position indicator indicating whether the cap is at a correctly closed position, based on the positional relationship between the protrusion and the position indicator.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 28, 2017
    Applicants: DENSO WAVE INCORPORATED, ANIMAL STEM CELL
    Inventors: Koji KAMIYA, Wataru SAITO, Kazuhiro NAGAIKE
  • Publication number: 20170212154
    Abstract: According to one embodiment, a current detection circuit (12) includes: a detection resistor (Rs) provided between a solenoid valve (106) and a solenoid driver (11); an amplification unit (121) configured to amplify a detected voltage of the detection resistor (Rs); an AD converter (122) that is driven by a reference voltage (Vref) generated based on a reference current (Iref) and configured to convert an output voltage from the amplification unit (121) into a digital value and output the digital value as a detected current value (D1); and a correction unit configured to perform a correction on the detected current value (D1).
    Type: Application
    Filed: January 9, 2017
    Publication date: July 27, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Masanori OTSUKA, Wataru SAITO, Yoshitaka JINGU, Yasuhiko KOKAMI, Satoshi KONDO, Junya HORISHIMA
  • Publication number: 20170141224
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; a fifth semiconductor region; an insulating portion that is provided between the second semiconductor region and the fifth semiconductor region and between the third semiconductor region and the fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; a second electrode; and a third electrode that is provided on the third semiconductor region and electrically connected to the third semiconductor region and the gate electrode.
    Type: Application
    Filed: September 9, 2016
    Publication date: May 18, 2017
    Inventor: Wataru Saito
  • Publication number: 20170040414
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor region of a first conductivity type, a first insulating unit, a conductive unit, a stacked body, a fourth semiconductor region of a second conductivity type, a fifth semiconductor region of the first conductivity type, a gate electrode, and a gate insulating unit. The stacked body includes multiple second semiconductor regions of the first conductivity type and multiple third semiconductor regions of the second conductivity type. The multiple third semiconductor regions are connected to the conductive unit. The third semiconductor regions are provided alternately with the second semiconductor regions in a first direction from the first semiconductor region toward the portion of the first insulating unit. The gate electrode is provided on one other portion of the first insulating unit. The stacked body is positioned between the gate electrode and the conductive unit in a second direction.
    Type: Application
    Filed: January 19, 2016
    Publication date: February 9, 2017
    Inventor: Wataru Saito
  • Patent number: 9437728
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
  • Patent number: 9412857
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Wataru Saito, Toru Sugiyama
  • Patent number: 9391142
    Abstract: A semiconductor device of this embodiment includes: a first semiconductor layer including AlXGa1-XN; a second semiconductor layer provided above the first semiconductor layer, and including undoped or n-type AlYGa1-YN; a first and second electrodes provided above the second semiconductor layer; a third semiconductor layer provided above the second semiconductor layer between the first electrode and the second electrode, is at a distance from each of the first and second electrodes, and including p-type AlZGa1-ZN; a control electrode provided above the third semiconductor layer; a fourth semiconductor layer provided above the third semiconductor layer between the first electrode and the control electrode, is at a distance from the control electrode, and including n-type AlUGa1-UN; and a fifth semiconductor layer provided above a portion of the third semiconductor layer between the control electrode and the second electrode, is at a distance from the control electrode, and including n-type AlUGa1-UN.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Yasunobu Saito
  • Patent number: 9349721
    Abstract: A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: May 24, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Hiroaki Yamashita
  • Patent number: 9343536
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having a wider band gap than the first semiconductor layer, a source electrode and a drain electrode provided on the second semiconductor layer, wherein at least one of the source electrode and the drain electrode includes a plurality of protrusions on a side in contact with the second semiconductor layer, and a gate electrode provided between the source electrode and the drain electrode.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: May 17, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Kazuo Tsutsui, Hiroshi Iwai, Kuniyuki Kakushima, Hitoshi Wakabayashi
  • Publication number: 20160079373
    Abstract: A semiconductor device includes a compound semiconductor layer, an insulating element, and a conductive element. The conductive element includes a plurality of conductive regions which are spaced from the compound semiconductor layer in a first direction. The insulating element is provided between the compound semiconductor layer and the conductive element. A length of each of the plurality of conductive regions in a second direction which intersects the first direction becomes longer the farther the individual one of the plurality of conductive regions is spaced from the compound semiconductor layer.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 17, 2016
    Inventors: Takeshi UCHIHARA, Wataru SAITO, Takaaki YASUMOTO, Naoko YANASE
  • Publication number: 20160043213
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 11, 2016
    Inventors: Wataru SAITO, Syotaro ONO, Toshiyuki NAKA, Shunji TANIUCHI, Miho WATANABE, Hiroaki YAMASHITA
  • Publication number: 20160043187
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having a wider band gap than the first semiconductor layer, a source electrode and a drain electrode provided on the second semiconductor layer, wherein at least one of the source electrode and the drain electrode includes a plurality of protrusions on a side in contact with the second semiconductor layer, and a gate electrode provided between the source electrode and the drain electrode.
    Type: Application
    Filed: February 13, 2015
    Publication date: February 11, 2016
    Inventors: Wataru Saito, Kazuo Tsutsui, Hiroshi Iwai, Kuniyuki Kakushima, Hitoshi Wakabayashi
  • Patent number: 9196721
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
  • Patent number: RE46799
    Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 17, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Wataru Saito, Ichiro Omura, Kozo Kinoshita
  • Patent number: RE47641
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu Yamaguchi, Wataru Saito, Ichiro Omura, Masaru Izumisawa