Patents by Inventor Wataru Sakamoto

Wataru Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183507
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuyuki Sekine, Tatsuya Kato, Fumitaka Arai, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa, Akio Kaneko
  • Patent number: 11152385
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: October 19, 2021
    Assignee: Kioxia Corporation
    Inventors: Tatsuya Kato, Wataru Sakamoto, Fumitaka Arai
  • Publication number: 20210300109
    Abstract: A rotary drive device in a mobile body includes a main wheel and a pair of drive assemblies opposing each other and each driving the main wheel. The main wheel includes driven rollers. One of the pair of drive assemblies includes a motor, a motor case, a drive force transmission, and driving rollers. The driving rollers are in the drive force transmission along a circumferential direction, and contact at least a portion of the driven rollers from one side of the rotary drive device of the axial direction. The drive force transmission rotates to transmit a drive force of the motor to the main wheel via the driving rollers. At least a portion of the motor case opposes at least a portion of the driving rollers in the axial direction.
    Type: Application
    Filed: March 30, 2021
    Publication date: September 30, 2021
    Inventors: Taihei TSUBONE, Kyohei HAIZUMI, Wataru YADA, Tomokazu SAKAMOTO, Takeshi ECHIZENYA, Seiji KATO
  • Publication number: 20210288057
    Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 16, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi NAGASHIMA, Tatsuya KATO, Wataru SAKAMOTO
  • Publication number: 20210282991
    Abstract: The vehicle is provided with a lift unit includes a fixed base (21) supported by a vehicle body frame, a movable base (22) connected to a seat base supporting a seat (4), and supported by the fixed base so as to be movable between a lowered position and a reference position higher than the lowered position relative to the fixed base, an engagement device (23) configured to selectively retain the movable base to the fixed base at the reference position, an electric lift mechanism (24) configured to move the movable base vertically relative to the seat base, and a control unit (6) controlling the engagement device and the electric lift mechanism.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 16, 2021
    Inventors: Wataru YADA, Tomokazu SAKAMOTO, Masaki GOTO, Takeshi ECHIZENYA
  • Publication number: 20210233775
    Abstract: A method of high-throughput dry etching of silicon oxide and silicon nitride materials by in-situ autocatalyst formation. The method includes providing a substrate having a film thereon in a process chamber, the film containing silicon oxide, silicon nitride, or both silicon oxide and silicon nitride, introducing an etching gas containing fluorine and hydrogen, and setting a gas pressure in the process chamber that is between about 1 mTorr and about 300 mTorr, and a substrate temperature that is below about ?30° C. The method further includes plasma-exciting the etching gas, and exposing the film to the plasma-excited etching gas, where the film is continuously etched during the exposing.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 29, 2021
    Inventors: Du Zhang, Manabu Iwata, Yu-Hao Tsai, Takahiro Yokoyama, Yanxiang Shi, Yoshihide Kihara, Wataru Sakamoto, Mingmei Wang
  • Patent number: 11049868
    Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Nagashima, Tatsuya Kato, Wataru Sakamoto
  • Publication number: 20210188586
    Abstract: Systems and methods for dryer rollers of a print system with increasing wrap angles. In one embodiment a dryer includes a turning device configured to rotate about an axis, and to guide a web of print media. The dryer also includes rollers configured to transport the web from an entrance of the dryer to the turning device. The rollers include a series of three or more rollers positioned in the dryer to consecutively increase an amount of contact area with the web as the web travels toward the turning device.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Applicant: Ricoh Company, Ltd.
    Inventors: Stuart J. Boland, Scott R. Johnson, Wataru Sakamoto
  • Patent number: 11018148
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 25, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Watanabe, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Wataru Sakamoto, Tatsuya Kato
  • Publication number: 20210134822
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 6, 2021
    Applicant: Toshiba Memory Corporation
    Inventor: Wataru SAKAMOTO
  • Patent number: 10991708
    Abstract: A semiconductor device of the embodiment includes a stacked body, a first insulating layer, first and second staircase portions 2, and a second insulating layer 46. The stacked body includes a first electrode layer 41 (WLDD) and a second electrode layer 41 (SGD). The first and second staircase portions 2 are provided in a first end portion 101 a second end region 102. The second insulating layer 46 extends in the X-direction. The second insulating layer divides the second electrode layer 41 (SGD) in the X-direction direction. A length L1 in the X-direction of the second insulating layer 46 is longer than a length L2 in the x-direction of the second electrode layer 41 (SGD) and shorter than a length L3 in the X-direction of the first electrode layer 41 (WLDD).
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru Sakamoto, Hiroshi Nakaki, Hanae Ishihara
  • Patent number: 10923488
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: February 16, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Wataru Sakamoto
  • Patent number: 10910392
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Publication number: 20200381294
    Abstract: There is formed, on a stack formed by alternately stacking an oxide film and a nitride film or an oxide film and a polysilicon film on a substrate, a hard mask in which two or more kinds of lines made of mutually different materials are arranged in order. Then, a photoresist is applied onto the hard mask. Furthermore, the photoresist is trimmed until one line is exposed from the end of the hard mask. Moreover, one line of the hard mask exposed beneath the photoresist is etched. Furthermore, a part of the stack exposed beneath the hard mask is etched. The etching of the photoresist, the hard mask, and the stack is repeated while changing etching conditions.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Kazuo KIBI, Akihiro TAKAHASHI, Wataru SAKAMOTO
  • Publication number: 20200357810
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru SAKAMOTO, Ryota SUZUKI, Tatsuya OKAMOTO, Tatsuya KATO, Fumitaka ARAI
  • Patent number: 10763272
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru Sakamoto, Ryota Suzuki, Tatsuya Okamoto, Tatsuya Kato, Fumitaka Arai
  • Patent number: 10686045
    Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto
  • Publication number: 20200124521
    Abstract: The present invention relates to a fluorescent probe for flow cytometry that includes a carrier molecule and porphyrin bound to the carrier molecule and in which an excitation wavelength of the fluorescent probe for flow cytometry is in a range of 350 to 650 nm. The present invention also relates to a method for screening fluorescence-labeled cells using a flow cytometer that includes a step of fluorescently labeling cells with a fluorescent probe for flow cytometry and a step of screening fluorescence-labeled cells labeled with the fluorescent probe for flow cytometry using a flow cytometer, and in which the screening of the fluorescence-labeled cells using a flow cytometer is performed by irradiating the fluorescence-labeled cells with excitation light with a wavelength of 350 to 650 nm and detecting fluorescence.
    Type: Application
    Filed: February 10, 2017
    Publication date: April 23, 2020
    Inventors: Koichiro HAYASHI, Wataru SAKAMOTO, Toshinobu YOGO, Hiroki MARUOKA
  • Publication number: 20200111804
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Wataru SAKAMOTO
  • Publication number: 20200051991
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima