Patents by Inventor Wataru Yokozeki

Wataru Yokozeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6870788
    Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: March 22, 2005
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Patent number: 6822912
    Abstract: A semiconductor device that includes macro cells and a fuse of smaller size. Each macro cell includes normal blocks and a redundant block. Each normal block includes circuits each having a predetermined function. The redundant block has the same function as the normal blocks have. If one of the normal blocks does not work well, it will be replaced with the redundant block. The fuse holds information for specifying the normal block to be replaced with the redundant block included in the macro cell. This fuse is shared by a plurality of macro cells.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: November 23, 2004
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Publication number: 20040208046
    Abstract: At switching normal operation mode to low power mode, a first switch disconnects a virtual power supply line and a normal power supply line in response to activation of a switch control signal. The power supply voltage to a first circuit block connected to the virtual power supply line is suspended during the low power mode. A second switch of a floating prevention circuit connects a node between output of the first circuit block and input of a second circuit block to a first voltage line in response to inactivation of the switch control signal during the low power mode. This prevents the input of the second circuit block from floating even without the power supply voltage supplied to the first circuit block, and therefore prevents feedthrough current from flowing through the second circuit block, which enables reduction in power consumption during the low power mode.
    Type: Application
    Filed: February 17, 2004
    Publication date: October 21, 2004
    Inventor: Wataru Yokozeki
  • Publication number: 20040190323
    Abstract: A semiconductor memory device comprises a memory cell array, a decoder unit selecting a word line of the memory cell array, a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line, a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location, and a timing control unit determining timing of activation and deactivation of an internal control signal.
    Type: Application
    Filed: October 28, 2003
    Publication date: September 30, 2004
    Inventors: Tetsuo Ashizawa, Wataru Yokozeki
  • Publication number: 20040173830
    Abstract: A nonvolatile semiconductor memory device includes a substrate, a plurality of transistors formed on the substrate to constitute a latch, a plate line, and a pair of capacitors each including a lower electrode, a ferroelectric film, and an upper electrode, the pair of capacitors being provided in a layer situated above the substrate and below a metal wiring layer in which the plate line is formed.
    Type: Application
    Filed: December 17, 2003
    Publication date: September 9, 2004
    Inventors: Wataru Yokozeki, Akio Itoh
  • Patent number: 6741505
    Abstract: A semiconductor memory device has a dummy bit line, a reference voltage generating circuit, a comparator circuit, and a timing signal generating circuit. The dummy bit line has a load equal to a load of a bit line, and the reference voltage generating circuit generates a reference voltage. The comparator circuit compares a potential of the dummy bit line with the reference voltage, and the timing signal generating circuit generates various kinds of timing signals based on an output of the comparator circuit. The semiconductor memory device simultaneously selects a plurality of dummy memory cells and connects the selected dummy memory cells to the dummy bit line, and adjusts the potential of the dummy bit line.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: May 25, 2004
    Assignee: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Patent number: 6741487
    Abstract: A semiconductor memory that reduces the amount of power consumed by an entire unit by decreasing a charging/discharging current. A row direction selection circuit selects predetermined memory cell groups in a row direction in response to a row input address signal. A column direction selection circuit selects predetermined memory cell groups in a column direction in response to a column input address signal. Connection-disconnection circuits connect a divided bit line corresponding to a column selected by the column direction selection circuit of divided bit lines connected to memory cell groups, respectively, selected by the row direction selection circuit to the corresponding common bit line and do not connect divided bit lines corresponding to the other columns.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: May 25, 2004
    Assignee: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Patent number: 6738281
    Abstract: Inputs of two buffer circuits which constitute a latch circuit receive different voltages due to a capacitance coupling effect of ferroelectric capacitors or capacitance division of the ferroelectric capacitors, before connected with power source. After the power turns on, a switch control circuit activates switch control signals when a first plate voltage rises to a predetermined voltage. Switch circuits turn on in response to the activation of the switch control signals, and connect power source terminals of the buffer circuits to a power source line. At this time, input voltages of the buffer circuits are different from each other, and therefore, logic data is written into the latch circuit according to each of the input voltages. As a result of this, data held in the latch circuit before turning-off of the power can be reproduced without fail.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: May 18, 2004
    Assignee: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Publication number: 20040085846
    Abstract: An integrated circuit has a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, and further has a latch circuit, connected to the second power line, which is constituted by a transistor of a second threshold voltage which is lower than the first threshold voltage, and a ferroelectric capacitor for storing data held in the latch circuit in accordance with the polarization direction of a ferroelectric film thereof. The integrated circuit also comprises a control signal generating circuit which, when returning to an active mode from the sleep mode, generates a plate signal for driving a terminal of the ferroelectric capacitor to generate a voltage in the latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the sleep switch to conduct to thereby activate the latch circuit following the driving of the ferroelectric capacitor.
    Type: Application
    Filed: August 26, 2003
    Publication date: May 6, 2004
    Inventors: Wataru Yokozeki, Shoichi Masui
  • Publication number: 20040085798
    Abstract: A nonvolatile data storage circuit has a data holding circuit having a storage node, and a plurality of ferroelectric capacitors one electrodes of which are connected to the storage node. In this nonvolatile data storage circuit, in store operations to write data from the data holding circuit to the ferroelectric capacitors, the timing of at least the rising or the falling of plate signals supplied to the other electrodes of the plurality of ferroelectric capacitors, is made different. During store operation, the timing of the plate signals applied to the plurality of ferroelectric capacitors connected to the storage node is shifted, so that coupling noise between the ferroelectric capacitors is dispersed and can be reduced, and data inversion of the data holding circuit can be prevented.
    Type: Application
    Filed: August 26, 2003
    Publication date: May 6, 2004
    Inventors: Wataru Yokozeki, Shoichi Masui
  • Publication number: 20040032768
    Abstract: First buffers of a first driver circuit generate voltages to be supplied to word lines, respectively. Second buffers of a second driver circuit operate in synchronization with the first buffers to generate voltages to be supplied to first substrate lines, respectively. Each second buffer, upon access to memory cells, supplies a voltage for lowering the threshold values of transfer transistors and driver transistors to its corresponding first substrate line, and supplies thereto a voltage for raising the threshold values of the transfer transistors and the driver transistors during standby. This can improve the operation speed at the time of accessing the memory cells and reduce the leak current during standby. This results in shortening the access time during the operation of the semiconductor memory and reducing the standby current during standby.
    Type: Application
    Filed: July 30, 2003
    Publication date: February 19, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuo Ashizawa, Wataru Yokozeki
  • Publication number: 20040021160
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 5, 2004
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Publication number: 20040001384
    Abstract: A semiconductor device that includes macro cells and a fuse of smaller size. Each macro cell includes normal blocks and a redundant block. Each normal block includes circuits each having a predetermined function. The redundant block has the same function as the normal blocks have. If one of the normal blocks does not work well, it will be replaced with the redundant block. The fuse holds information for specifying the normal block to be replaced with the redundant block included in the macro cell. This fuse is shared by a plurality of macro cells.
    Type: Application
    Filed: May 30, 2003
    Publication date: January 1, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Patent number: 6657229
    Abstract: A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers, which are in separated patterns.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: December 2, 2003
    Assignee: United Microelectronics Corporation
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Patent number: 6594190
    Abstract: A semiconductor device includes two latch circuits, each of which latches a corresponding one of complementary data outputs supplied from an amplifier circuit, and includes only one intervening gate from an input thereof to an output thereof, the latch circuits being reset by an activation signal that activates the amplifier circuit.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: July 15, 2003
    Assignee: Fujitsu Limited
    Inventors: Wataru Yokozeki, Kazuto Furumochi
  • Publication number: 20030123276
    Abstract: Inputs of two buffer circuits which constitute a latch circuit receive different voltages due to a capacitance coupling effect of ferroelectric capacitors or capacitance division of the ferroelectric capacitors, before connected with power source. After the power turns on, a switch control circuit activates switch control signals when a first plate voltage rises to a predetermined voltage. Switch circuits turn on in response to the activation of the switch control signals, and connect power source terminals of the buffer circuits to a power source line. At this time, input voltages of the buffer circuits are different from each other, and therefore, logic data is written into the latch circuit according to each of the input voltages. As a result of this, data held in the latch circuit before turning-off of the power can be reproduced without fail.
    Type: Application
    Filed: October 15, 2002
    Publication date: July 3, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Wataru Yokozeki
  • Publication number: 20030122578
    Abstract: A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide desired logic functions. Those building blocks can be dynamically reconfigured by changing the selection of configuration data stored in the device's integral configuration memories. The configuration memories are divided into groups, so that they can be loaded concurrently with multiple configuration data streams. To protect the content of configuration memories from unauthorized access, the device employs an authentication mechanism that uses security IDs stored in the configuration memories. The device has a memory controller to provide an appropriate power supply sequence for ferroelectric memory cells to ensure the reliable data retention when the device is powered up or shut down.
    Type: Application
    Filed: December 24, 2002
    Publication date: July 3, 2003
    Inventors: Shoichi Masui, Michiya Oura, Tsuzumi Ninomiya, Wataru Yokozeki, Kenji Mukaida
  • Publication number: 20030090951
    Abstract: A semiconductor memory that reduces the amount of power consumed by an entire unit by decreasing a charging/discharging current. A row direction selection circuit selects predetermined memory cell groups in a row direction in response to a row input address signal. A column direction selection circuit selects predetermined memory cell groups in a column direction in response to a column input address signal. Connection-disconnection circuits connect a divided bit line corresponding to a column selected by the column direction selection circuit of divided bit lines connected to memory cell groups, respectively, selected by the row direction selection circuit to the corresponding common bit line and do not connect divided bit lines corresponding to the other columns.
    Type: Application
    Filed: July 26, 2002
    Publication date: May 15, 2003
    Applicant: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Publication number: 20030090944
    Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.
    Type: Application
    Filed: July 22, 2002
    Publication date: May 15, 2003
    Applicant: Fujitsu Limited
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Patent number: 6556472
    Abstract: The present invention is a static RAM comprising a memory cell array having memory cells located at intersections of word lines and bit lines, and a sense amplifier for amplifying a voltage of the bit lines; this static RAM further comprising: dummy memory cells selected when the word line is selected; a dummy bit line connected to the dummy memory cells; a timing signal generating circuit for generating a timing control signal in response to a change in potential of the dummy bit line; and a dummy memory cell selecting circuit for, in response to a selection of a word line in a word line group including a plurality of the word lines, selecting the dummy memory cell shared by the word line group.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: April 29, 2003
    Assignee: Fujitsu Limited
    Inventor: Wataru Yokozeki