Patents by Inventor Wataru Yokozeki

Wataru Yokozeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6552946
    Abstract: An address generating circuit having: a first switch transistor, a second switch transistor, a fuse element, and a power-ON reset circuit for outputting a first reset signal for controlling ON/OFF conditions of the first switch transistor and a second reset signal for controlling ON/OFF conditions of the second switch transistor. The address generating circuit also includes a latch circuit for latching and outputting a predetermined potential corresponding to a cut-off or a no cut-off condition of the fuse element. The first reset signal turns ON the first switch transistor during a first period immediately after the power supply is turned ON and always holds the first switch transistor in the OFF condition after the first period is completed. Furthermore, the second reset signal turns ON the second switch transistor at least during a second period after the first period and always holds the second switch transistor in the OFF condition after the second period is completed.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: April 22, 2003
    Assignee: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Publication number: 20030063493
    Abstract: A semiconductor memory device has a dummy bit line, a reference voltage generating circuit, a comparator circuit, and a timing signal generating circuit. The dummy bit line has a load equal to a load of a bit line, and the reference voltage generating circuit generates a reference voltage. The comparator circuit compares a potential of the dummy bit line with the reference voltage, and the timing signal generating circuit generates various kinds of timing signals based on an output of the comparator circuit. The semiconductor memory device simultaneously selects a plurality of dummy memory cells and connects the selected dummy memory cells to the dummy bit line, and adjusts the potential of the dummy bit line.
    Type: Application
    Filed: March 22, 2002
    Publication date: April 3, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Wataru Yokozeki
  • Patent number: 6504217
    Abstract: A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or the like is formed on the polysilicon film. The impurities are thermally diffused to form shallow-junctions of source/drain having low-concentration impurities. Lead-out electrodes having a high-impurity concentration can be formed without impeding formation of the source and drain. The refractory metal film is converted into a silicide with the resistance at the interface between the polysilicon film and the silicide kept lowered.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: January 7, 2003
    Assignee: United Microelectronics Corporation
    Inventor: Wataru Yokozeki
  • Publication number: 20020186579
    Abstract: The present invention is a static RAM comprising a memory cell array having memory cells located at intersections of word lines and bit lines, and a sense amplifier for amplifying a voltage of the bit lines; this static RAM further comprising: dummy memory cells selected when the word line is selected; a dummy bit line connected to the dummy memory cells; a timing signal generating circuit for generating a timing control signal in response to a change in potential of the dummy bit line; and a dummy memory cell selecting circuit for, in response to a selection of a word line in a word line group including a plurality of the word lines, selecting the dummy memory cell shared by the word line group.
    Type: Application
    Filed: January 8, 2002
    Publication date: December 12, 2002
    Applicant: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Publication number: 20020141273
    Abstract: An address generating circuit having: a first switch transistor, a second switch transistor, a fuse element, and a power-ON reset circuit for outputting a first reset signal for controlling ON/OFF conditions of the first switch transistor and a second reset signal for controlling ON/OFF conditions of the second switch transistor. The address generating circuit also includes a latch circuit for latching and outputting a predetermined potential corresponding to a cut-off or a no cut-off condition of the fuse element. The first reset signal turns ON the first switch transistor during a first period immediately after the power supply is turned ON and always holds the first switch transistor in the OFF condition after the first period is completed. Furthermore, the second reset signal turns ON the second switch transistor at least during a second period after the first period and always holds the second switch transistor in the OFF condition after the second period is completed.
    Type: Application
    Filed: January 9, 2002
    Publication date: October 3, 2002
    Applicant: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Publication number: 20020079543
    Abstract: A semiconductor device includes two latch circuits, each of which latches a corresponding one of complementary data outputs supplied from an amplifier circuit, and includes only one intervening gate from an input thereof to an output thereof, the latch circuits being reset by an activation signal that activates the amplifier circuit.
    Type: Application
    Filed: May 25, 2001
    Publication date: June 27, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Wataru Yokozeki, Kazuto Furumochi
  • Patent number: 6411559
    Abstract: A semiconductor memory device which comprises a memory cell array having a plurality of memory cells, complementary data bus lines connected to said memory cells in said memory cell array and a sense amplifier. The sense amplifier is connected to the memory cells through the complementary data bus lines and amplifies a difference between current values on said complementary data bus lines associated with a logical value stored in the memory cell. The sense amplifier has a positive feedback circuit having a plurality of differential pairs constructed by transistors.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: June 25, 2002
    Assignee: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Patent number: 6243319
    Abstract: The output of a pre-decoder 10A is provided, on one side, to a main decoder 22 with the input of negative logic and on the other side, to a main decoder 21 with the input of positive logic through an inverting circuit 40. The number of gate stages from the output of the pre-decoder 10A to the output of the main decoder 21 is three which is equal to the number of gate stages from the output of the pre-decoder 10A to the output of the main decoder 22.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: June 5, 2001
    Assignee: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Patent number: 6066894
    Abstract: A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or the like is formed on the polysilicon film. The impurities are thermally diffused to form shallow-junctions of source/drain having low-concentration impurities. Lead-out electrodes having a high-impurity concentration can be formed without impeding formation of the source and drain. The refractory metal film is converted into a silicide with the resistance at the interface between the polysilicon film and the silicide kept lowered.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: May 23, 2000
    Assignee: United Microelectronics Corporation
    Inventor: Wataru Yokozeki