Patents by Inventor Water Lur
Water Lur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8062536Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: March 22, 2010Date of Patent: November 22, 2011Assignee: United Microelectronics Corp.Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Publication number: 20100173490Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: ApplicationFiled: March 22, 2010Publication date: July 8, 2010Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Patent number: 7718079Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: November 20, 2001Date of Patent: May 18, 2010Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, Wen Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Patent number: 7514014Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: April 11, 2000Date of Patent: April 7, 2009Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, W. B. Shieh, J. Y. Wu, Water Lur, Shih-Wei Sun
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Patent number: 7449407Abstract: An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.Type: GrantFiled: November 15, 2002Date of Patent: November 11, 2008Assignee: United Microelectronics CorporationInventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
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Patent number: 7378740Abstract: An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.Type: GrantFiled: August 2, 2005Date of Patent: May 27, 2008Assignee: United Microelectronics Corp.Inventors: Tri-Rung Yew, Yimin Huang, Water Lur, Shih-Wei Sun
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Patent number: 7271101Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: December 22, 2005Date of Patent: September 18, 2007Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Patent number: 7253095Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.Type: GrantFiled: July 11, 2005Date of Patent: August 7, 2007Assignee: United Microelectronics CorporationInventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
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Publication number: 20070076339Abstract: An air gap structure substantially reduces undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.Type: ApplicationFiled: November 20, 2006Publication date: April 5, 2007Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
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Patent number: 7138329Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.Type: GrantFiled: November 15, 2002Date of Patent: November 21, 2006Assignee: United Microelectronics CorporationInventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
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Patent number: 7105426Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.Type: GrantFiled: April 15, 2005Date of Patent: September 12, 2006Assignee: United Microelectronics Corp.Inventors: Joey Lai, Water Lur
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Publication number: 20060180832Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.Type: ApplicationFiled: April 25, 2006Publication date: August 17, 2006Inventors: Joey Lai, Water Lur
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Patent number: 7078346Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: July 29, 2004Date of Patent: July 18, 2006Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Patent number: 7064048Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.Type: GrantFiled: October 17, 2003Date of Patent: June 20, 2006Assignee: United Microelectronics Corp.Inventors: Joey Lai, Water Lur
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Publication number: 20060099824Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: ApplicationFiled: December 22, 2005Publication date: May 11, 2006Inventors: Chih-Chien Liu, Ta-Shan Tseng, W.B. Shieh, J.Y. Wu, Water Lur, Shih-Wei Sun
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Patent number: 7037802Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.Type: GrantFiled: September 13, 2004Date of Patent: May 2, 2006Assignee: United Microelectronics CorporationInventors: Ming-Sheng Yang, Juan-Yuan Wu, Water Lur
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Patent number: 7018906Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.Type: GrantFiled: November 9, 2004Date of Patent: March 28, 2006Assignee: United Microelectronics CorporationInventors: Coming Chen, Juan-Yuan Wu, Water Lur
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Patent number: 7005363Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.Type: GrantFiled: March 18, 2005Date of Patent: February 28, 2006Assignee: United Microelectronics Corp.Inventors: Joey Lai, Water Lur
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Patent number: 7001713Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.Type: GrantFiled: November 21, 2001Date of Patent: February 21, 2006Assignee: United Microelectronics, Corp.Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
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Publication number: 20060014388Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti—along with layers of Co—are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.Type: ApplicationFiled: September 12, 2005Publication date: January 19, 2006Inventors: Water Lur, David Lee, Kuang-Chih Wang