Patents by Inventor Wee-Guan Tan
Wee-Guan Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11196385Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.Type: GrantFiled: February 18, 2020Date of Patent: December 7, 2021Assignee: Silicon Laboratories Inc.Inventors: Ruifeng Sun, Ricky Setiawan, Ben Wee-Guan Tan
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Publication number: 20210257970Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.Type: ApplicationFiled: February 18, 2020Publication date: August 19, 2021Inventors: Ruifeng Sun, Ricky Setiawan, Ben Wee-Guan Tan
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Patent number: 9065437Abstract: A circuit for driving a transistor includes a drive circuit, a first voltage boost circuit and a second voltage boost circuit. The drive circuit has a first specific node, a second specific node, and a third specific node coupled to a control node of the transistor. The drive circuit is arranged for coupling the first specific node to the third specific node according to at least a voltage of the first specific node and a voltage of the second specific node in order to charge the control node. The first voltage boost circuit is coupled between the first specific node and a connection node of the transistor, and is arranged for boosting the voltage of the first specific node. The second voltage boost circuit is coupled between the first specific node and the second specific node, and is arranged for boosting the voltage of the second specific node.Type: GrantFiled: April 21, 2014Date of Patent: June 23, 2015Assignee: MediaTek Singapore Pte. Ltd.Inventors: Wee Guan Tan, Siong Siew Yong
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Publication number: 20140320177Abstract: A circuit for driving a transistor includes a drive circuit, a first voltage boost circuit and a second voltage boost circuit. The drive circuit has a first specific node, a second specific node, and a third specific node coupled to a control node of the transistor. The drive circuit is arranged for coupling the first specific node to the third specific node according to at least a voltage of the first specific node and a voltage of the second specific node in order to charge the control node. The first voltage boost circuit is coupled between the first specific node and a connection node of the transistor, and is arranged for boosting the voltage of the first specific node. The second voltage boost circuit is coupled between the first specific node and the second specific node, and is arranged for boosting the voltage of the second specific node.Type: ApplicationFiled: April 21, 2014Publication date: October 30, 2014Applicant: MediaTek Singapore Pte. Ltd.Inventors: Wee Guan Tan, Siong Siew Yong
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Publication number: 20110199752Abstract: The invention relates to a mount (10; 12; 14) for mounting an electrical appliance (20). The invention also relates to a stand comprising the mount, to fastening means (60) for an electrical appliance, to an electrical appliance comprising the fastening means, to a toolkit (200) for mounting the electrical appliance, and to a method of mounting the electrical appliance. The mount comprises a base (30; 32; 34) which comprises connecting means (50) for connecting the base (30; 32; 34) to a surface (100) or for connecting the base to a stand. The base is configured for distributing a weight of the electrical appliance across a part of the surface or to the stand.Type: ApplicationFiled: September 17, 2009Publication date: August 18, 2011Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Tim Kern, Wee Guan Tan
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Patent number: 7944292Abstract: A feedback circuit disposed across input and output terminals of an amplifier is adapted so as not inject DC current back into the input terminal of the amplifier. The feedback circuit includes, in part, first and second current sources, a transistor, and a resistive load. The first current source supplies current to one of the terminals of the transistor in communication with an input terminal of the amplifier. The second current source receives this current and diverts it to a voltage supply. The transistor is maintained in the active region of operation. The resistive load has a first terminal in communication with an output terminal of the amplifier and a second terminal in communication with the transistor. The DC voltages at the two terminals of the resistive load are substantially equal so as to inhibit DC current flow therethrough.Type: GrantFiled: May 2, 2008Date of Patent: May 17, 2011Assignee: Marvell International Ltd.Inventor: Ben Wee-Guan Tan
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Patent number: 7372329Abstract: A feedback circuit disposed across input and output terminals of an amplifier is adapted so as not inject DC current back into the input terminal of the amplifier. The feedback circuit includes, in part, first and second current sources, a transistor, and a resistive load. The first current source supplies current to one of the terminals of the transistor in communication with an input terminal of the amplifier. The second current source receives this current and diverts it to a voltage supply. The transistor is maintained in the active region of operation. The resistive load has a first terminal in communication with an output terminal of the amplifier and a second terminal in communication with the transistor. The DC voltages at the two terminals of the resistive load are substantially equal so as to inhibit DC current flow therethrough.Type: GrantFiled: August 16, 2006Date of Patent: May 13, 2008Assignee: Marvell International Ltd.Inventor: Ben Wee-Guan Tan
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Publication number: 20060208768Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.Type: ApplicationFiled: May 22, 2006Publication date: September 21, 2006Inventors: Afshin Momtaz, Wee-Guan Tan, Armond Hairapetian
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Publication number: 20060164127Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.Type: ApplicationFiled: March 6, 2006Publication date: July 27, 2006Inventors: Afshin Momtaz, Wee-Guan Tan, Almond Hairapetian
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Patent number: 7049856Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.Type: GrantFiled: January 6, 2005Date of Patent: May 23, 2006Assignee: Broadcom CorporationInventors: Afshin Momtaz, Wee-Guan Tan, Armond Hairapetian
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Publication number: 20050122137Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.Type: ApplicationFiled: January 6, 2005Publication date: June 9, 2005Inventors: Afshin Momtaz, Wee-Guan Tan, Armond Hairapetian
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Patent number: 6888381Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.Type: GrantFiled: October 1, 2001Date of Patent: May 3, 2005Assignee: Broadcom CorporationInventors: Afshin Momtaz, Wee-Guan Tan, Armond Hairapetian
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Publication number: 20030062928Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.Type: ApplicationFiled: October 1, 2001Publication date: April 3, 2003Inventors: Afshin Momtaz, Wee-Guan Tan, Armond Hairapetian
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Patent number: D1018975Type: GrantFiled: September 1, 2021Date of Patent: March 19, 2024Assignee: Dyson Technology LimitedInventors: Emily Mary Menzies, James Robert Alexander Fisher, Wee Guan Tan, Nicklaus Yu, David Oliver Williams, Phey Hong Soh, Stephen Benjamin Courtney