Abstract: A method of making an integrated includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.

Abstract: A muscle tone assessment device includes a pedal, a front force sensor and a back force sensor arranged at the pedal, and a judgment unit connected to the sensors. The judgment unit obtains a front force standard deviation, a back force standard deviation, a front force deviation and a back force deviation from the sensing results, and obtains a first and a second threshold value from the front force standard deviation and the back force standard deviation. The front force standard deviation and the back force standard deviation are the standard deviations of the front force signal and the back force signal within a first time interval. The front force deviation and the back force deviation represent the deviation of the front force signal and the back force signal in a second time interval. In addition, the present invention further provides a muscle tone assessment method.

Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

Abstract: A method includes doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

Abstract: Main technical features of a sealing mechanism of a pressure vessel provided by the invention are a sealing unit for airtightly combining with the vessel, and a combination unit for positioning the sealing unit in the airtight combination state, and there are common structures disposed between constituent elements of the sealing unit and the combination unit, so that the sealing unit and the combination unit can be combined with each other in order to facilitate use and storage and to avoid losing or missing parts.

Abstract: A method (of forming a semiconductor device) including forming cell regions (in alternating first and second rows having first and second heights) including forming a majority of the cell regions in the first rows including: limiting a height of the majority of the cell regions to be single-row cell regions that span corresponding single one of the first rows but do not extend therebeyond; and forming a minority of the cell regions correspondingly in at least the first rows including reducing widths of the multi-row cell regions to be smaller than comparable single-row cell regions; and expanding heights of the minority of the cell regions to be multi-row cell regions, each of the multi-row cell regions spanning a corresponding single first row and at least a corresponding second row such that cell region densities of the second rows are at least about forty percent.

Abstract: A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Abstract: A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.

Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

Abstract: A layout method includes: providing a library comprising a first cell and a second cell, wherein each of the first and second cells includes: a first active region and a second active region extending in a first direction; a first cell-edge gate structure and a second cell-edge gate structure extending in a second direction; and a third cell-edge gate structure and a fourth cell-edge gate structure extending in the second direction, wherein each of the first and second cell further includes one of a tie-off conductive line or a tie-off marker layer on each of the first and second cell-edge gate structures. The layout method further includes: generating a design layout by placing and abutting the first cell and the second cell; updating the design layout by performing a post-processing step on the tie-off conductive line and the tie-off marker layer of each of the first and second cells.

Abstract: For a mapping application, a method for reporting a problem related to a map displayed by the mapping application is described. The method identifies a mode in which the mapping application is operating. The method identifies a set of types of problems to report based on the identified mode. The method displays, in a display area of the mapping application, a graphical user interface (GUI) page that includes a set of selectable user interface (UI) items that represent the identified set of types of problems.

Abstract: A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

Abstract: The present disclosure provides a micro light emitting diode display including a metal substrate, a plurality of micro light emitting diode chips on the metal substrate, a plurality of light absorbing layers on the metal substrate between the micro light emitting diode chips, a light conversion layer above the micro light emitting diode chips, and a cover plate above the light conversion layer, where sidewalls of the micro light emitting diode chips are separated by a gap, and where a contact angle of the light absorbing layers is between 0 degree and 30 degrees.

Abstract: An electronic device and a method for determining medical images are provided. The method includes: obtaining an input image; inputting the input image into a first machine learning model to generate a labeled image, wherein the labeled image includes a plurality of area images; inputting the labeled image into a second machine learning model to generate a plurality of area determination data corresponding to the plurality of area images; and displaying a determination result including the plurality of area determination data.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A method of making a semiconductor structure includes defining a first recess in an insulation layer. The method further includes forming a protection layer along a sidewall of the first recess. The method further includes forming a first conductive line in the first recess and in direct contact with the protection layer. The method further includes depositing a first insulation material over the first conductive line. The method further includes defining a second recess in the first insulation material. The method further includes forming a second conductive line in the second recess. The method further includes forming a via extending from the second conductive line, wherein the via directly contacts a sidewall of the protection layer.

Abstract: A server for knowledge recommendation for defect review. The server includes a processor electronically coupled to an electronic storage device storing a plurality of knowledge files related to wafer defects. The processor is configured to execute a set of instruction to cause the server to: receive a request for knowledge recommendation for inspecting an inspection image from a defect classification server; search for a knowledge file in the electronic storage device that matches the inspection image; and transmit the search result to the defect classification server.

Abstract: A screwdriver structure may include a tool rod and a rotating head which are adapted to connect together, and the tool rod is configured to be connected with a handle when the rotating head is separated from the tool rod, so as to use the screwdriver for different situations. The tool rod has a hand-holdable main body which has one end connecting to an extending rod, and a connecting column formed at the other end of the main body has the outer diameter smaller than the main body, and at least a flange is formed on the outer periphery of the connecting column. The extending rod comprises a sleeve at the end thereof to connect a tool head or a bolt.