Patents by Inventor Wei Cheng Hsu

Wei Cheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170309672
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Publication number: 20170207176
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Patent number: 9704910
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 9627326
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Publication number: 20160327489
    Abstract: A system for physiologic parameter examination includes a housing and a test-strip tray. The housing includes a carrying cavity disposed on a top surface of the housing and including a window. The carrying cavity is configured to receive a portable electronic device having an image-capturing component. The image-capturing component corresponds to the window. The test-strip tray is movably disposed in the housing and located below the carrying cavity. The test-strip tray is configured to carry at least one test strip. The image-capturing component is adapted to capture a test reaction of the test strip through the window. A method for test strip recognition and interpretation applicable to the system is also provided.
    Type: Application
    Filed: February 26, 2016
    Publication date: November 10, 2016
    Inventors: Fu-Chiang Chou, Yung-Lung Chang, Fu-Cheng Fan, Yi-Chi Lin, Chin-Hua Hsieh, Wei-Cheng Hsu, Syuan-He Shih
  • Publication number: 20160276285
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Application
    Filed: May 26, 2016
    Publication date: September 22, 2016
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Publication number: 20160204149
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 9355964
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Patent number: 9293502
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 9281334
    Abstract: A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Publication number: 20150255400
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 10, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Publication number: 20150214266
    Abstract: A complementary metal oxide semiconductor (CMOS) image sensor and a method for fabricating the same are provided. An example CMOS image sensor includes first active regions of a semiconductor substrate, where the first active regions are arranged in rows or columns. Photosensitive regions are formed in the first active regions. The CMOS image sensor also includes second active regions of the semiconductor substrate that are interposed between the first active regions. Each of the second active regions includes a device isolation region formed by doping the semiconductor substrate with impurities. Each of the second active regions also includes a channel region of a field effect transistor (FET) that is formed within the device isolation region and is configured to connect source and drain regions of the FET. At least one control gate is formed over each of the second active regions.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: MIN-FENG KAO, WEI-CHENG HSU, TZU-JUI WANG, HSIAO-HUI TSENG, TZU-HSUAN HSU, JEN-CHENG LIU, JHY-JYI SZE, DUN-NIAN YAUNG
  • Publication number: 20150041945
    Abstract: A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 12, 2015
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Publication number: 20150028403
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 8878242
    Abstract: A device includes a device isolation region formed into a semiconductor substrate, the device isolation region having gaps for photo-sensitive devices, a dummy gate structure formed over the substrate, the dummy gate structure comprising at least one structure that partially surrounds a doped pickup region formed into the device isolation region, and a via connected to the doped pickup region.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 8513587
    Abstract: An image sensor the image sensor comprising an absorption layer disposed on a silicon substrate, the absorption layer having at least one of SiGe or Ge, and an antireflection layer disposed directly thereon.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: August 20, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Jui Wang, Hsiao-Hui Tseng, Wei-Cheng Hsu, Dun-Nian Yaung, Jen-Cheng Liu
  • Publication number: 20120187282
    Abstract: An image sensor the image sensor comprising an absorption layer disposed on a silicon substrate, the absorption layer having at least one of SiGe or Ge, and an antireflection layer disposed directly thereon.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Jui WANG, Hsiao-Hui TSENG, Wei-Cheng HSU, Dun-Nian YAUNG, Jen-Cheng LIU
  • Patent number: 8184237
    Abstract: The display device of the present invention includes a housing, a display module, and a signal receiver. The housing has a front opening; the display module includes a backlight module. A display area is formed on the display module corresponding to the front opening. The signal receiver is disposed in the display module and is located outside the display area, to receive signals.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: May 22, 2012
    Assignee: Qisda Corporation
    Inventors: Wei-Cheng Hsu, Chieh-Yuan Cheng
  • Publication number: 20100020260
    Abstract: The display device of the present invention includes a housing, a display module, and a signal receiver. The housing has a front opening; the display module includes a backlight module. A display area is formed on the display module corresponding to the front opening. The signal receiver is disposed in the display module and is located outside the display area, to receive signals.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 28, 2010
    Applicant: QISDA CORPORATION
    Inventors: Wei-Cheng Hsu, Chieh-Yuan Cheng
  • Patent number: 7644717
    Abstract: A hair clip and hairpin combining device includes a pin member pivotally coupled to a plate with a pivot axle and for allowing the plate to be rotated relative to the pin member between an open working position and a folded clamping position, and a spring member coupled between the ears and the flaps for maintaining the plate and the pin member either at the open working position as a hairpin or at the folded clamping position as a hair clip, and thus for allowing the hair clip and hairpin combining device to be changeable between the hair clip and the hairpin or for being used as either a hair clip or a hairpin.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: January 12, 2010
    Inventor: Wei Cheng Hsu