Patents by Inventor Wei-Chung Lo

Wei-Chung Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004816
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Publication number: 20210082810
    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 18, 2021
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Tao-Chih Chang, Yu-Min Lin, Sheng-Tsai Wu
  • Publication number: 20210066189
    Abstract: A package substrate includes a substrate, an interposer and an insulating protective layer. The substrate has a first surface and a second surface opposing to the first surface. The first surface includes a plurality of first conductive pads. The interposer is disposed on the first surface of the substrate such that the first conductive pads are partially covered by the interposer. The interposer includes a plurality of penetrating conductive vias electrically connected to the substrate. The insulating protective layer is disposed on the first surface of the substrate and surrounding the interposer. The insulating protective layer includes at least one penetrating conductive column, wherein a first width of the respective penetrating conductive column is greater than a second width of each of the penetrating conductive vias of the interposer.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 4, 2021
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong HSIEH
  • Patent number: 10867907
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 15, 2020
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Publication number: 20200075519
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 5, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Publication number: 20190252345
    Abstract: A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 15, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Tao-Chih Chang, Wei-Chung Lo
  • Patent number: 10276908
    Abstract: An electromagnetic wave transmission board comprises a substrate. The substrate comprises a first dielectric layer and a second dielectric layer, and the first dielectric layer is stacked on the second dielectric layer. The first dielectric layer and the second dielectric layer together form a wave guiding space. The wave guiding space is configured for transmitting electromagnetic wave.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 30, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Wei Huang, Shih-Hsien Wu, Wei-Chung Lo
  • Publication number: 20180323143
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 8, 2018
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 10068847
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 4, 2018
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Publication number: 20180183127
    Abstract: An electromagnetic wave transmission board comprises a substrate. The substrate comprises a first dielectric layer and a second dielectric layer, and the first dielectric layer is stacked on the second dielectric layer. The first dielectric layer and the second dielectric layer together form a wave guiding space. The wave guiding space is configured for transmitting electromagnetic wave.
    Type: Application
    Filed: March 24, 2017
    Publication date: June 28, 2018
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Wei HUANG, Shih-Hsien WU, Wei-Chung LO
  • Patent number: 9931813
    Abstract: A bonding structure and a method of fabricating the same are provided. A first substrate having a first bonding element and a second substrate having a second bonding element are provided, wherein at least one of the first bonding element and the second bonding element is formed with an alloy. A bonding process is performed to bond the first bonding element with the second bonding element, wherein a diffusion liner is generated at the exposed, non-bonded surface of the bonding structure.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 3, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Kuan-Neng Chen, Wei-Chung Lo, Cheng-Ta Ko
  • Publication number: 20170194249
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 6, 2017
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 9647029
    Abstract: In an embodiment, a light emitting device comprises a light emitting diode chip and a spherical extending electrode. The light emitting diode chip includes a semiconductor epitaxial structure, a first electrode and a second electrode. The first electrode and the second electrode are disposed on two opposite sides of the semiconductor epitaxial structure, respectively. The first electrode is disposed between the semiconductor epitaxial structure and the spherical extending electrode, and the spherical extending electrode is electrically connected to the semiconductor epitaxial structure electrically through the first electrode. The volume of the spherical extending electrode is greater than that of the light emitting diode chip.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 9, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Chung Lo, Yu-Wei Huang, Tao-Chih Chang, Chih-Ming Shen
  • Publication number: 20170104027
    Abstract: In an embodiment, a light emitting device comprises a light emitting diode chip and a spherical extending electrode. The light emitting diode chip includes a semiconductor epitaxial structure, a first electrode and a second electrode. The first electrode and the second electrode are disposed on two opposite sides of the semiconductor epitaxial structure, respectively. The first electrode is disposed between the semiconductor epitaxial structure and the spherical extending electrode, and the spherical extending electrode is electrically connected to the semiconductor epitaxial structure electrically through the first electrode. The volume of the spherical extending electrode is greater than that of the light emitting diode chip.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 13, 2017
    Inventors: Wei-Chung Lo, Yu-Wei Huang, Tao-Chih Chang, Chih-Ming Shen
  • Patent number: 9485874
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: November 1, 2016
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 9252054
    Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 2, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Tsai Wu, Heng-Chieh Chien, John H. Lau, Yu-Lin Chao, Wei-Chung Lo
  • Patent number: 9111774
    Abstract: A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: August 18, 2015
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
  • Publication number: 20150076682
    Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 19, 2015
    Inventors: Sheng-Tsai WU, Heng-Chieh CHIEN, John H. LAU, Yu-Lin CHAO, Wei-Chung LO
  • Patent number: 8915634
    Abstract: A plane light source including a circuit substrate, a plurality of sets of side-view light-emitting devices (LEDs), and a diffusive light-guiding layer is provided. The side-view LEDs are arranged in array over the circuit substrate and are electrically connected with the circuit substrate. The diffusive light-guiding layer covers the side-view LEDs, wherein the diffusive light-guiding layer includes a plurality of diffusive light-guiding units arranged in array and connected to each other. Each of the diffusive light-guiding units is respectively corresponded to illumination coverage of one set of side-view LEDs. Each set of side-view LEDs at least includes two side-view LEDs for emitting light respectively along two different directions and towards into one single diffusive light-guiding units.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: December 23, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Kai Hsu, Yu-Hua Chen, Wei-Chung Lo
  • Patent number: 8810031
    Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 19, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee