Patents by Inventor Wei-Chung Lo
Wei-Chung Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150076682Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.Type: ApplicationFiled: September 12, 2014Publication date: March 19, 2015Inventors: Sheng-Tsai WU, Heng-Chieh CHIEN, John H. LAU, Yu-Lin CHAO, Wei-Chung LO
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Patent number: 8915634Abstract: A plane light source including a circuit substrate, a plurality of sets of side-view light-emitting devices (LEDs), and a diffusive light-guiding layer is provided. The side-view LEDs are arranged in array over the circuit substrate and are electrically connected with the circuit substrate. The diffusive light-guiding layer covers the side-view LEDs, wherein the diffusive light-guiding layer includes a plurality of diffusive light-guiding units arranged in array and connected to each other. Each of the diffusive light-guiding units is respectively corresponded to illumination coverage of one set of side-view LEDs. Each set of side-view LEDs at least includes two side-view LEDs for emitting light respectively along two different directions and towards into one single diffusive light-guiding units.Type: GrantFiled: August 21, 2012Date of Patent: December 23, 2014Assignee: Industrial Technology Research InstituteInventors: Chao-Kai Hsu, Yu-Hua Chen, Wei-Chung Lo
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Patent number: 8810031Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.Type: GrantFiled: December 30, 2010Date of Patent: August 19, 2014Assignee: Industrial Technology Research InstituteInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Publication number: 20140117557Abstract: A package substrate and a method for forming the package substrate are disclosed. The package substrate includes an interposer having a plurality of conductive through vias and a first insulating layer formed on the sidewalls of the conductive through vias, a second insulating layer formed on one side of the interposer, and a plurality of conductive vias formed in the second insulating layer and electrically connected to the conductive through vias. By increasing the thickness of the first insulating layer, the face diameter of the conductive through vias can be reduced, and the layout density of the conductive through vias in the interposer can thus be increased.Type: ApplicationFiled: August 13, 2013Publication date: May 1, 2014Applicants: UNIMICRON TECHNOLOGY CORPORATION, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Hua CHEN, Wei-Chung LO, Dyi-Chung HU, Chang-Hong HSIEH
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Publication number: 20140102777Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.Type: ApplicationFiled: August 26, 2013Publication date: April 17, 2014Applicants: Unimicron Technology Corporation, Industrial Technology Research InstituteInventors: Yu-Hua CHEN, Wei-Chung LO, Dyi-Chung HU, Chang-Hong HSIEH
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Publication number: 20140084413Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a top surface and a bottom surface opposing the top surface; an insulating protective layer formed on the top surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and passive components provided on or embedded in the interposer. By integrating the passive components into the package substrate, when a chip is provided on the interposer, the conductive path between the chip and the passive components can be shortened, and the pins of the chip have a stable voltage. Therefore, the overall electrical performance is enhanced.Type: ApplicationFiled: August 13, 2013Publication date: March 27, 2014Applicants: UNIMICRON TECHNOLOGY CORPORATION, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Hua CHEN, Wei-Chung LO, Dyi-Chung HU, Chang-Hong HSIEH
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Patent number: 8679891Abstract: A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.Type: GrantFiled: September 6, 2013Date of Patent: March 25, 2014Assignee: National Chiao Tung UniversityInventors: Kuan-Neng Chen, Cheng-Ta Ko, Wei-Chung Lo
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Publication number: 20140004630Abstract: A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.Type: ApplicationFiled: September 6, 2013Publication date: January 2, 2014Applicant: National Chiao Tung UniversityInventors: KUAN-NENG CHEN, CHENG-TA KO, WEI-CHUNG LO
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Patent number: 8536613Abstract: A heterostructure contains an IC and an LED. An IC and an LED are initially provided. The IC has at least one first electric-conduction block and at least one first connection block. The IC electrically connects with the first electric-conduction block. The first face of the LED has at least one second electric-conduction block and at least one second connection block. The LED electrically connects to the second electric-conduction block. Subsequently, the first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block. The first electric-conduction block is electrically connected with the second electric-conduction block and forms a heterostructure. The system simultaneously provides functions of heat radiation and electric communication for the IC and LED resulting in a high-density, multifunctional heterostructure.Type: GrantFiled: September 2, 2011Date of Patent: September 17, 2013Assignee: National Chiao Tung UniversityInventors: Kuan-Neng Chen, Cheng-Ta Ko, Wei-Chung Lo
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Publication number: 20130128610Abstract: A plane light source including a circuit substrate, a plurality of sets of side-view light-emitting devices (LEDs), and a diffusive light-guiding layer is provided. The side-view LEDs are arranged in array over the circuit substrate and are electrically connected with the circuit substrate. The diffusive light-guiding layer covers the side-view LEDs, wherein the diffusive light-guiding layer includes a plurality of diffusive light-guiding units arranged in array and connected to each other. Each of the diffusive light-guiding units is respectively corresponded to illumination coverage of one set of side-view LEDs. Each set of side-view LEDs at least includes two side-view LEDs for emitting light respectively along two different directions and towards into one single diffusive light-guiding units.Type: ApplicationFiled: August 21, 2012Publication date: May 23, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chao-Kai Hsu, Yu-Hua Chen, Wei-Chung Lo
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Publication number: 20120313133Abstract: A heterostructure contains an IC and an LED. An IC and an LED are initially provided. The IC has at least one first electric-conduction block and at least one first connection block. The IC electrically connects with the first electric-conduction block. The first face of the LED has at least one second electric-conduction block and at least one second connection block. The LED electrically connects to the second electric-conduction block. Subsequently, the first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block. The first electric-conduction block is electrically connected with the second electric-conduction block and forms a heterostructure. The system simultaneously provides functions of heat radiation and electric communication for the IC and LED resulting in a high-density, multifunctional heterostructure.Type: ApplicationFiled: September 2, 2011Publication date: December 13, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: KUAN-NENG CHEN, CHENG-TA KO, WEI-CHUNG LO
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Patent number: 8304666Abstract: A plurality of coaxial leads is made within a single via in a circuit substrate to enhance the density of vertical interconnection so as to match the demand for higher density multi-layers circuit interconnection between top circuit layer and bottom circuit layer of the substrate. Coaxial leads provide electromagnetic interference shielding among the plurality of coaxial leads in a single via.Type: GrantFiled: May 19, 2009Date of Patent: November 6, 2012Assignee: Industrial Technology Research InstituteInventors: Cheng-Ta Ko, Min-Lin Lee, Wei-Chung Lo, Shur-Fen Liu, Jinn-Shing King, Shinn-Juh Lai, Yu-Hua Chen
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Publication number: 20120178212Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.Type: ApplicationFiled: March 20, 2012Publication date: July 12, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 8164165Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.Type: GrantFiled: June 20, 2006Date of Patent: April 24, 2012Assignee: Industrial Technology Research InstituteInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 8049330Abstract: A structure of light emitting diode (LED) wafer-level chip scale packaging (WL-CSP) is disclosed. The process of making the same is also provided in this invention. The LED CSP utilizes the through hole metal filling to enhance heat conduction between the LED die and its carrier substrate. The CSP structure is achieved by bonding pre-processed through-hole-filling carrier substrate against the flip-chip LED wafer.Type: GrantFiled: November 23, 2005Date of Patent: November 1, 2011Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, Wei-Chung Lo, Li-Cheng Shen
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Patent number: 8039935Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.Type: GrantFiled: January 11, 2007Date of Patent: October 18, 2011Assignee: Industrial Technology Research InstituteInventors: Shu-Ming Chang, Lee-Cheng Shen, Wei-Chung Lo
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Publication number: 20110195273Abstract: A bonding structure and a method of fabricating the same are provided. A first substrate having a first bonding element and a second substrate having a second bonding element are provided, wherein at least one of the first bonding element and the second bonding element is formed with an alloy. A bonding process is performed to bond the first bonding element with the second bonding element, wherein a diffusion liner is generated at the exposed, non-bonded surface of the bonding structure.Type: ApplicationFiled: May 6, 2010Publication date: August 11, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kuan-Neng Chen, Wei-Chung Lo, Cheng-Ta Ko
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Publication number: 20110156249Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.Type: ApplicationFiled: December 30, 2010Publication date: June 30, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 7948072Abstract: A wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate.Type: GrantFiled: July 25, 2008Date of Patent: May 24, 2011Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, Shu-Ming Chang, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee, Chi-Shih Chang
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Publication number: 20100163296Abstract: A plurality of coaxial leads is made within a single via in a circuit substrate to enhance the density of vertical interconnection so as to match the demand for higher density multi-layers circuit interconnection between top circuit layer and bottom circuit layer of the substrate. Coaxial leads provide electromagnetic interference shielding among the plurality of coaxial leads in a single via.Type: ApplicationFiled: May 19, 2009Publication date: July 1, 2010Applicant: Industrial Technology Research InstituteInventors: Cheng-Ta Ko, Min-Lin Lee, Wei-Chung Lo, Shur-Fen Liu, Jinn-Shing King, Shinn-Juh Lai, Yu-Hua Chen