Patents by Inventor Wei Han Koo

Wei Han Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081455
    Abstract: A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Chan Lam Cha, Wei Han Koo, Thorsten Meyer, Klaus Schiess, Guan Choon Matthew Nelson Tee
  • Patent number: 11075185
    Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 27, 2021
    Assignee: Infineon Technologies AG
    Inventors: Chii Shang Hong, Ivan Nikitin, Wei Han Koo, Chiew Li Tai
  • Patent number: 10978380
    Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies AG
    Inventors: Chii Shang Hong, Wei Han Koo, Chiew Li Tai
  • Publication number: 20200350272
    Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.
    Type: Application
    Filed: September 18, 2019
    Publication date: November 5, 2020
    Inventors: Chii Shang Hong, Ivan Nikitin, Wei Han Koo, Chiew Li Tai
  • Publication number: 20200350238
    Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 5, 2020
    Inventors: Chii Shang Hong, Wei Han Koo, Chiew Li Tai
  • Publication number: 20200343205
    Abstract: A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Chan Lam Cha, Wei Han Koo, Thorsten Meyer, Klaus Schiess, Guan Choon Matthew Nelson Tee
  • Patent number: 10727151
    Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies AG
    Inventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoeck, Gilles Delarozee
  • Patent number: 10396018
    Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Chan Lam Cha, Wei Han Koo, Andreas Kucher, Theng Chao Long
  • Publication number: 20190164873
    Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 30, 2019
    Inventors: Chau Fatt Chiang, Chan Lam Cha, Wei Han Koo, Andreas Kucher, Theng Chao Long
  • Publication number: 20180342438
    Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoek, Gilles Delarozee