Patents by Inventor Wei-Lun Huang
Wei-Lun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12074118Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.Type: GrantFiled: June 13, 2023Date of Patent: August 27, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia Hsiu Huang, Chun Chen Chen, Wei Chih Cho, Shao-Lun Yang
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Patent number: 12054699Abstract: A perfusion cell culture device includes a driving module and a plurality of cell culture modules. The driving module includes a driving source connecting opening and a chamber. The chamber and the driving source connecting opening are connected. Each of the culture modules includes a fluid channel, a first elastic element, two flow direction controlling units and a cell culture zone. The fluid channel is disposed above the chamber, the first elastic element is disposed between the fluid channel and the chamber, the two flow direction controlling units are respectively disposed on two ends of the fluid channel and connected to the fluid channel selectively, and the cell culture zone is connected to the two flow direction controlling units.Type: GrantFiled: June 22, 2021Date of Patent: August 6, 2024Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Wei-Han Lai, Jen-Huang Huang, Yu-Lun Lu
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Patent number: 12046596Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.Type: GrantFiled: October 6, 2021Date of Patent: July 23, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Huang, Chia-Ling Wang, Chia-Wen Lu, Ping-Hung Chiang
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Patent number: 12045499Abstract: A storage device sharing system and a storage device sharing method are provided. The storage device sharing system includes a storage device, a first chip and a second chip. The first chip and the second chip are configured to enter a toggle mode and an arbitration mode. In the toggle mode, the first chip that acts as the master controls the arbitration potential to a first control potential and a second control potential, and communicates with the storage device in response to the arbitration potential being the first control potential, and the second chip that acts as a slave communicates with the storage device in response to the arbitration potential being the second control potential.Type: GrantFiled: July 29, 2022Date of Patent: July 23, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chun-Chieh Chan, Wei-Lun Huang, Chia-Fen Lin
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Publication number: 20240085611Abstract: A front light module includes a light guide sheet and a light bar. The light guide sheet has two light receiving laterals, a fold line, a first pattern area, and a second pattern area respectively located on two sides of the fold line. One light receiving lateral is protruded to form first taper sets, and the other is protruded to form second taper sets. The second pattern area is superimposed on the first pattern area, and the first and second tapers set are engaged and coplanar to form a light incident surface after folding along the fold line. The light bar provides light toward the light incident surface, the first pattern area is lit by the odd positions of the light bar via the first taper sets, and the second pattern area is lit by the even positions of the light bar via the second taper sets.Type: ApplicationFiled: June 8, 2023Publication date: March 14, 2024Inventors: JIN-WEI TONG, HAO LU, FAN-WEI WU, WEI-LUN HUANG
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Patent number: 11758100Abstract: A device may provide, to a camera and a projector of a portable projection mapping device, first instructions for calibrating the camera and the projector, and may receive, based on the first instructions, calibration parameters for the camera and the projector. The device may calculate a stereo calibration between the camera and the projector based on the calibration parameters, and may provide, to the camera, second instructions for recognizing a reference instrument associated with the portable projection mapping device. The device may receive, based on the second instructions, binocular images, and may determine additional parameters based on the binocular images. The device may determine recognition parameters for recognizing the reference instrument, based on the binocular images and the additional parameters.Type: GrantFiled: September 9, 2020Date of Patent: September 12, 2023Assignee: The Johns Hopkins UniversityInventors: Mehran Armand, Shuya Liu, Wei-Lun Huang, Austin Shin
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Publication number: 20230231035Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.Type: ApplicationFiled: February 17, 2022Publication date: July 20, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Huang, Chia-Ling Wang, Chia-Wen Lu, Ta-Wei Chiu, Ping-Hung Chiang
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Publication number: 20230223306Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.Type: ApplicationFiled: February 15, 2022Publication date: July 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ta-Wei Chiu, Ping-Hung Chiang, Chia-Wen Lu, Chia-Ling Wang, Wei-Lun Huang
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Publication number: 20230207620Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.Type: ApplicationFiled: January 18, 2022Publication date: June 29, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ling Wang, Ping-Hung Chiang, Wei-Lun Huang, Chia-Wen Lu, Ta-Wei Chiu
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Publication number: 20230133879Abstract: A storage device sharing system and a storage device sharing method are provided. The storage device sharing system includes a storage device, a first chip and a second chip. The first chip and the second chip are configured to enter a toggle mode and an arbitration mode. In the toggle mode, the first chip that acts as the master controls the arbitration potential to a first control potential and a second control potential, and communicates with the storage device in response to the arbitration potential being the first control potential, and the second chip that acts as a slave communicates with the storage device in response to the arbitration potential being the second control potential.Type: ApplicationFiled: July 29, 2022Publication date: May 4, 2023Inventors: CHUN-CHIEH CHAN, WEI-LUN HUANG, CHIA-FEN LIN
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Publication number: 20230080968Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.Type: ApplicationFiled: October 6, 2021Publication date: March 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Huang, Chia-Ling Wang, Chia-Wen Lu, Ping-Hung Chiang
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Patent number: 11573628Abstract: A smart mat includes a stepping potential generation unit, a computing processor and a transmission processor for sensing the stepping direction of a stepper to control the operation of a device. The stepping potential generation unit includes an upper mat, an isolating airgap layer, a lower mat and at least one high-resistance strips. When the stepper stands on the smart mat to press the stepping potential generation unit, a part of the stepping potential generation unit is pressed by an open-circuit state to form a closed circuit and generate a potential. The computing processor uses the distributed position of each potential and the time sequence of distributing each potential to compute and analyse a potential stepping process distribution area to obtain a stepping direction, so as to control the operation of the device through the transmission processor.Type: GrantFiled: August 27, 2021Date of Patent: February 7, 2023Assignee: CERADEX CORPORATIONInventors: Chen-Yuan Su, Liang-Tai Tsai, Wei-Lun Huang
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Publication number: 20230005658Abstract: A coupled inductor having a body, wherein a first electrode and a second electrode are connected to a first coil, and a third electrode and a fourth electrode are connected to a second coil, wherein a first horizontal line segment passing through the first electrode and the second electrode and a second horizontal line segment passing through the third electrode and the fourth electrode crosses each other at a location inside the periphery of a bottom surface of the body.Type: ApplicationFiled: June 30, 2022Publication date: January 5, 2023Inventors: Wei-Lun Huang, SEN-HUEI CHEN, Chi-Cheng Ma
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Publication number: 20220321851Abstract: A device may provide, to a camera and a projector of a portable projection mapping device, first instructions for calibrating the camera and the projector, and may receive, based on the first instructions, calibration parameters for the camera and the projector. The device may calculate a stereo calibration between the camera and the projector based on the calibration parameters, and may provide, to the camera, second instructions for recognizing a reference instrument associated with the portable projection mapping device. The device may receive, based on the second instructions, binocular images, and may determine additional parameters based on the binocular images. The device may determine recognition parameters for recognizing the reference instrument, based on the binocular images and the additional parameters.Type: ApplicationFiled: September 9, 2020Publication date: October 6, 2022Applicant: The Johns Hopkins UniversityInventors: Mehran ARMAND, Shuya LIU, Wei-Lun HUANG, Austin SHIN
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Patent number: 11425564Abstract: A system for integrating wireless service providers' core networks with Wi-Fi radios using a Wireless Services Gateway (WSG). The WSG can allow wireless device users to seamlessly connect to a network such as the internet using both cellular phone antennae as well as Wi-Fi radio antennae while still utilizing their preferred wireless service provider's core network system of billing, authenticating and policy decision making. This system can allow for data transmission of wireless devices through Wi-Fi instead of through cellular antennae, thus increasing bandwidth and data transmission rates.Type: GrantFiled: December 11, 2020Date of Patent: August 23, 2022Assignee: ARRIS Enterprises LLCInventors: Hemant Bhatnagar, Wayne Chuu, Chetan Hebbalae, Wei-Lun Huang, Rajesh Kaliaperumal, William Kish, Yi-Nan Li, Ronald Mok, Vijikumar Nagaraja, Venkatarao Palli, Yogesh Ranade, Ming-Jye Sheu, Henry Tzeng, You-Lin Yan, Thomas Yu
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Patent number: 11422964Abstract: An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port. The first configuration channel detection module is coupled to the first interface port through a first configuration channel pair, and configured to, after being communicated through a USB specification, detect a first configuration channel signal of a first input signal group to determine a signal type of the first input signal group, and control the first UFP physical layer module to output the first input signal group with a first signal configuration according to the signal type of the first input signal group.Type: GrantFiled: July 7, 2020Date of Patent: August 23, 2022Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chun-Chieh Chan, Wei-Lun Huang, Chia-Lung Hung, Yung-Ming Lin
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Publication number: 20220181070Abstract: A magnetic device, comprising a body and a coil disposed in the body, wherein a terminal part of the conductive wire forming the coil comprises a first portion and a second portion, wherein the first portion is exposed from the body for forming an electrode, wherein the second portion of the terminal part is deformed for increasing the distance between the terminal part of the conductive wire and the coil for preventing a short circuit.Type: ApplicationFiled: December 3, 2021Publication date: June 9, 2022Inventors: YuLun Chang, SEN-HUEI CHEN, WEI-LUN HUANG
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Publication number: 20220075446Abstract: A smart mat includes a stepping potential generation unit, a computing processor and a transmission processor for sensing the stepping direction of a stepper to control the operation of a device. The stepping potential generation unit includes an upper mat, an isolating airgap layer, a lower mat and at least one high-resistance strips. When the stepper stands on the smart mat to press the stepping potential generation unit, a part of the stepping potential generation unit is pressed by an open-circuit state to form a closed circuit and generate a potential. The computing processor uses the distributed position of each potential and the time sequence of distributing each potential to compute and analyse a potential stepping process distribution area to obtain a stepping direction, so as to control the operation of the device through the transmission processor.Type: ApplicationFiled: August 27, 2021Publication date: March 10, 2022Inventors: CHEN-YUAN SU, LIANG-TAI TSAI, WEI-LUN HUANG
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Publication number: 20210133136Abstract: An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port.Type: ApplicationFiled: July 7, 2020Publication date: May 6, 2021Inventors: CHUN-CHIEH CHAN, WEI-LUN HUANG, CHIA-LUNG HUNG, YUNG-MING LIN
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Patent number: 10984607Abstract: One exemplary implementation involves performing operations at a device with one or more processors, a camera, and a computer-readable storage medium, such as a desktop computer, laptop computer, tablet, or mobile phone. The device receives a data object corresponding to three dimensional (3D) content from a separate device. The device receives input corresponding to a user selection to view the 3D content in a computer generated reality (CGR) environment, and in response, displays the CGR environment at the device. To display the CGR environment the device uses the camera to capture images and constructs the CGR environment using the data object and the captured images.Type: GrantFiled: March 28, 2019Date of Patent: April 20, 2021Assignee: Apple Inc.Inventors: Norman N. Wang, Wei Lun Huang, David Lui, Tyler L. Casella, Ross R. Dexter