Abstract: A semiconductor device includes a substrate, a gate stack, a first gate spacer and a second gate spacer, a first source/drain region and a second source/drain region, a first conductive feature and a second conductive feature, and a first contact plug and a second contact plug. The first conductive feature and the second conductive feature are over the first source/drain region and the second source/drain region, respectively. The first conductive cap and the second conductive cap are over the first conductive feature and the second conductive feature, respectively. The first contact plug and the second contact plug are over the first conductive cap and the second conductive cap, respectively, in which the first contact plug is separated from the first gate spacer, and the second contact plug is in contact with a sidewall and a top surface of the second gate spacer.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, a gate stack, a gate spacer, a conductive feature, and a conductive cap. The substrate has a source/drain region. The gate stack is on the substrate. The gate spacer is alongside the gate stack. The conductive feature is on the source/drain region. The conductive cap is on the conductive feature and has a top in a position lower than a top of the gate spacer.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.

Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

Abstract: A charging control method includes the following. (a) An electrical state of a battery set is obtained. (b) Whether the electrical state is greater than a first electrical state threshold is determined and charging control based on a first charging mode or a second charging mode on the battery set is performed accordingly. (c) During the charging control on the battery set, at least one temperature difference value is determined based on temperature values of the battery set at different times. (d) Whether the temperature difference value is greater than a first temperature difference threshold is determined and whether to temporarily stop or continue the charging is determined accordingly. (e) During the charging control on the battery set, the electrical state is obtained, and whether the electrical state satisfies a fully-charged criterion is determined and whether to stop or continue the charging control is determined accordingly.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.

Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, a gate stack, a gate spacer, a conductive feature, and a conductive cap. The substrate has a source/drain region. The gate stack is on the substrate. The gate spacer is alongside the gate stack. The conductive feature is on the source/drain region. The conductive cap is on the conductive feature and has a top in a position lower than a top of the gate spacer.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.

Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.

Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.

Abstract: A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.

Abstract: The present disclosure provides a method for generating a parameter pattern including: performing a plurality of measurements upon a plurality of regions on a surface of a workpiece to obtain a plurality of measured results; and deriving a parameter pattern according to the plurality of measured results by a computer; wherein the parameter pattern includes a plurality of regional parameter values corresponding to each of the plurality of regions on the surface of the workpiece. The present disclosure provides a Feed Forward semiconductor manufacturing method including: forming a layer with a desired pattern on a surface of a workpiece; deriving a control signal including a parameter pattern according to spatial dimension measurements against the layer with the desired pattern distributed over a plurality of regions of the surface of the workpiece; and performing an ion implantation on the surface of the workpiece according to the control signal.

Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.

Abstract: A method of forming a gate includes: forming a dummy gate; forming an inter layer dielectric (ILD) laterally adjacent to the dummy gate; doping a dopant into the dummy gate and the ILD, in which a surface dopant concentration of the dummy gate is lower than a surface dopant concentration of the ILD; removing the dummy gate to form a cavity after doping the dopant into the dummy gate and the ILD; and forming the gate in the cavity.