Abstract: Disclosed is a power storage device and method for discharging the same, which configures the power storage device to perform an electric power output under a discharging limit upon coupling with a load device and before any authentication is conducted. The discharging limit for the electric power output will be lifted only when an authentication result between the power storage device and the load device indicates a successful authentication.

Abstract: An electronic device includes a substrate, a plurality of first retaining walls, a second retaining wall, and a light emitting element. The first retaining walls are arranged on the substrate. The second retaining wall is arranged on the substrate and disposed within one of the first retaining walls. The light emitting element is arranged on the substrate and disposed between the second retaining wall and one of the first retaining walls adjacent to the second retaining wall. In a cross section, there are a first distance between the light emitting element and the one of the first retaining walls, and a second distance between the light emitting element and the second retaining wall, wherein the second distance is smaller than the first distance.

Abstract: The present disclosure provides a pharmaceutical composition including a solid dispersion containing a cap-dependent endonuclease inhibitor or a pharmaceutically acceptable salt thereof for oral administration.

Abstract: A TFT array substrate includes a bottom plate, a first metal layer, an insulating layer, a semiconductor layer, a second metal layer, and a transparent electrode layer. The first metal layer is located on the bottom plate. The insulating layer covers the bottom plate and the first metal layer. The semiconductor layer is located on the insulating layer and overlaps a first portion of the first metal layer. The second metal layer has a first portion on the semiconductor layer and a second portion on the insulating layer, and the second portion of the second metal layer overlaps a second portion of the first metal layer. A first portion of the transparent electrode layer is disposed along the first portion of the second metal layer, and a second portion of the transparent electrode layer is disposed along the second portion of the second metal layer.

Abstract: An e-paper display apparatus including an e-paper display panel is provided. The e-paper display panel includes multiple pixel circuits arranged in an array. Each of the pixel circuits includes a transistor device. The transistor device is an oxide thin-film transistor. A set of signal waveforms for driving the pixel circuits to display image pages includes multiple frames. In a low panel frequency mode, the number of the frames is less than ten.

Abstract: An e-paper display apparatus including an e-paper display panel is provided. The e-paper display panel includes a plurality of pixel circuits arranged in an array. Each of the pixel circuits includes a transistor device, a storage capacitor and a pixel capacitor. A data voltage is configured to drive the storage capacitor and the pixel capacitor, so as to drive the e-paper display panel to display image. The transistor device is an oxide thin-film transistor. An absolute value of the data voltage is greater than or equal to 20 voltages.

Abstract: An e-paper display apparatus including an e-paper display panel is provided. The e-paper display panel includes a plurality of pixel circuits arranged in an array. Each of the pixel circuits includes a transistor device, a storage capacitor and a pixel capacitor. A data voltage is configured to drive the storage capacitor and the pixel capacitor, so as to drive the e-paper display panel to display image. The transistor device is an oxide thin-film transistor. An absolute value of the data voltage is greater than or equal to 20 voltages.

Abstract: An e-paper display apparatus including an e-paper display panel is provided. The e-paper display panel includes multiple pixel circuits arranged in an array. Each of the pixel circuits includes a transistor device. The transistor device is an oxide thin-film transistor. A set of signal waveforms for driving the pixel circuits to display image pages includes multiple frames. In a low panel frequency mode, the number of the frames is less than ten.

Abstract: The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

Abstract: A driving circuit film configured to be bond at a periphery region of a display panel. The driving circuit film includes a flexible substrate, a gate driving circuit and a source driver. The gate driving circuit is disposed on the flexible substrate, and the gate driving circuit includes a Thin-Film Transistor. The source driver is disposed on the flexible substrate.

Abstract: An electronic device includes a substrate, a first wiring layer, an oxide insulating layer and a nitride insulating layer. The first wiring layer is disposed on the substrate and includes an outer metal layer. The outer metal layer contains at least 97 wt % molybdenum. The oxide insulating layer is disposed on the first wiring layer and touches the outer metal layer. The nitride insulating layer is disposed on the oxide insulating layer, where the thickness difference between the thickness of the oxide insulating layer and the thickness of the nitride insulating layer is greater than or equal to 250 nm.

Abstract: An electronic device includes a substrate, a wiring structure, an oxide insulating layer and a nitride insulating layer. The wiring structure is disposed on the substrate and includes an outer metal layer and an inner metal layer. The outer metal layer contains no molybdenum. The inner metal layer disposed between the outer metal layer and the substrate contains molybdenum. The oxide insulating layer is disposed on the wiring structure and directly touches the outer metal layer. The nitride insulating layer is disposed on the oxide insulating layer, where the oxide insulating layer is positioned between the nitride insulating layer and the outer metal layer.

Abstract: The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

Abstract: A sensitive device includes a plurality of first conductive nanostructures, a conductive layer and at least one electrode. The conductive layer covers the first conductive nanostructures. An intrinsic melting point of the conductive layer is higher than that of the first conductive nanostructures. At least one of the conductive layer and the first conductive nanostructures is sensitive to gas. The electrode is electrically connected to at least one of the first conductive nanostructures and the conductive layer.

Abstract: A trace structure of a display panel including a first metal layer and a second metal layer is provided. The first metal layer is configured to transmit a first voltage. The second metal layer is disposed under the first metal layer and configured to transmit a second voltage. The first metal layer and the second metal layer form the trace structure on the display panel, such that the trace structure has a capacitor structure. The trace structure is configured to connect a power input and a panel driver circuit.

Abstract: A proximity sensor includes a substrate, a light source, a finger electrode, an active layer, and a transparent electrode layer. The substrate has opposite top and bottom surfaces. The light source faces toward the bottom surface of the substrate. The finger electrode is located on the top surface of the substrate, and has finger portions and gaps between every two adjacent finger portions. The active layer covers the finger electrode, and is located in the gaps. The transparent electrode layer is located on the active layer. When the light source emits light, the light through the gaps sequentially passes through the active layer and the transparent electrode layer onto a reflective surface. The light is reflected by the reflective surface to form reflected light, and the reflected light passes through the transparent electrode layer and is received by the active layer.

Abstract: A driving substrate includes a substrate, at least one active device, a resistor, a first passivation layer and a second passivation layer. The active device including an oxide semiconductor layer and the resistor coupled to the active device are disposed on the substrate. The first passivation layer covers the active device, wherein a portion of the first passivation layer directly contacts to the oxide semiconductor layer such that the oxide semiconductor layer has a first conductivity. The second passivation layer covers the first passivation layer and the resistor, wherein a portion of the second passivation layer directly contacts to the resistor such that the resistor has a second conductivity. The first conductivity is different from the second conductivity.

Abstract: A memory structure includes a substrate, a gate electrode, a first isolation layer, a thin metal layer, indium gallium zinc oxide (IGZO) particles, a second isolation layer, an IGZO channel layer, and a source/drain electrode. The gate electrode is located on the substrate. The first isolation layer is located on the gate electrode. The thin metal layer is located on the first isolation layer, and has metal particles. The IGZO particles are located on the metal particles. The second isolation layer is located on the IGZO particles. The IGZO channel layer is located on the second isolation layer. The source/drain electrode is located on the IGZO channel layer.

Abstract: A trace structure of a display panel including a first metal layer and a second metal layer is provided. The first metal layer is configured to transmit a first voltage. The second metal layer is disposed under the first metal layer and configured to transmit a second voltage. The first metal layer and the second metal layer form the trace structure on the display panel, such that the trace structure has a capacitor structure. The trace structure is configured to connect a power input and a panel driver circuit.

Abstract: A sensing element includes a conductive substrate, a zinc oxide seed layer, a plurality of zinc oxide nanorods, a film with an electrical double layer, and an organic sensing layer. The zinc oxide seed layer is located on the conductive substrate. The zinc oxide nanorods extend from the zinc oxide seed layer. The film with the electrical double layer covers the zinc oxide nanorods. The organic sensing layer is located on the film with the electrical double layer.