Patents by Inventor Wei-Tsung Chen

Wei-Tsung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11187843
    Abstract: An electronic device is provided. The electronic device includes a backlight module. The backlight module includes a light-guiding plate and a light-guiding element, and the light-guiding element is disposed under the light-guiding plate. In addition, the light-guiding element has a protruding structure, and the protruding structure faces the light-guiding plate.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 30, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Tsung Hsu, Hui-Wen Su, Chun-Fang Chen
  • Publication number: 20210365729
    Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A second neural network for video stabilization is trained to generate stabilized HDR images in a time-dependent manner.
    Type: Application
    Filed: May 25, 2020
    Publication date: November 25, 2021
    Applicant: Novatek Microelectronics Corp.
    Inventors: Jen-Huan Hu, Wei-Ting Chen, Yu-Che Hsiao, Shih-Hsiang Lin, Po-Chin Hu, Yu-Tsung Hu, Pei-Yin Chen
  • Publication number: 20210288634
    Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.
    Type: Application
    Filed: April 14, 2020
    Publication date: September 16, 2021
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Cheng-Yang Tsai, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Yu-Lin Chen
  • Patent number: 11119139
    Abstract: An integrated circuit with antenna in package (AiP IC) testing apparatus is provided, and includes: a carrier board, a test socket, and a receiving antenna circuit board. The test socket is disposed on the carrier board and configured to carry an AiP IC which emits a wireless signal. The receiving antenna circuit board is adjacent to the test socket and configured to receive the wireless signal. The receiving antenna circuit board and the reflector are integrated into the AiP IC testing apparatus, so that the AiP IC testing apparatus can be used not only for testing a feedback signal transmitted by a test pin of the IC, but also for testing the wireless signal from the IC.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Shin-tsung Chen, Wei-cheng Wang
  • Patent number: 11120761
    Abstract: A driving substrate includes a substrate, at least one active device, a resistor, a first passivation layer and a second passivation layer. The active device including an oxide semiconductor layer and the resistor coupled to the active device are disposed on the substrate. The first passivation layer covers the active device, wherein a portion of the first passivation layer directly contacts to the oxide semiconductor layer such that the oxide semiconductor layer has a first conductivity. The second passivation layer covers the first passivation layer and the resistor, wherein a portion of the second passivation layer directly contacts to the resistor such that the resistor has a second conductivity. The first conductivity is different from the second conductivity.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 14, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Patent number: 11114570
    Abstract: A memory structure includes a substrate, a gate electrode, a first isolation layer, a thin metal layer, indium gallium zinc oxide (IGZO) particles, a second isolation layer, an IGZO channel layer, and a source/drain electrode. The gate electrode is located on the substrate. The first isolation layer is located on the gate electrode. The thin metal layer is located on the first isolation layer, and has metal particles. The IGZO particles are located on the metal particles. The second isolation layer is located on the IGZO particles. The IGZO channel layer is located on the second isolation layer. The source/drain electrode is located on the IGZO channel layer.
    Type: Grant
    Filed: April 12, 2020
    Date of Patent: September 7, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Ching-Fu Lin, Zong-Xuan Li, Wei-Tsung Chen
  • Publication number: 20210272527
    Abstract: A trace structure of a display panel including a first metal layer and a second metal layer is provided. The first metal layer is configured to transmit a first voltage. The second metal layer is disposed under the first metal layer and configured to transmit a second voltage. The first metal layer and the second metal layer form the trace structure on the display panel, such that the trace structure has a capacitor structure. The trace structure is configured to connect a power input and a panel driver circuit.
    Type: Application
    Filed: March 2, 2021
    Publication date: September 2, 2021
    Applicant: E Ink Holdings Inc.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Po-Hsin Lin
  • Patent number: 11041822
    Abstract: A sensing element includes a conductive substrate, a zinc oxide seed layer, a plurality of zinc oxide nanorods, a film with an electrical double layer, and an organic sensing layer. The zinc oxide seed layer is located on the conductive substrate. The zinc oxide nanorods extend from the zinc oxide seed layer. The film with the electrical double layer covers the zinc oxide nanorods. The organic sensing layer is located on the film with the electrical double layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 22, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Yu-Nung Mao, Hung-Chuan Liu, Zong-Xuan Li, Wei-Tsung Chen
  • Patent number: 10923068
    Abstract: A display device and a display driving circuit with electromagnetic interference suppression capability are provided. The display device includes a substrate, an active matrix, a display driver and a thin-film transistor (TFT) conditioning circuit. The active matrix disposed on the substrate includes multiple data lines, multiple gate lines and multiple pixels. The data lines intersect with the gate lines. The pixels are coupled to intersections of the data lines and the gate lines. The display driver disposed on the substrate generates signals for driving the data lines and/or the gate lines in response to a conditioned serial data clock. The TFT conditioning circuit disposed on the substrate is coupled to the display driver. The TFT conditioning circuit includes one or more TFTs, and attenuates an amplitude of a serial data clock in response to a predetermined gate bias to provide the conditioned serial data clock to the display driver.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 16, 2021
    Assignee: E INK HOLDINGS INC.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Yu-Lin Wang, Po-Hsin Lin
  • Patent number: 10879362
    Abstract: A transistor including a substrate, a source, a drain, an active portion, a fin-shaped gate, and an insulation layer is provided. The source is located on the substrate. The drain is located on the substrate. The active portion connects the source and the drain. The fin-shaped gate wraps the active portion. A first portion of the insulation layer separates the fin-shaped gate from the active portion, a second portion of the insulation layer separates the fin-shaped gate from the substrate, a third portion of the insulation layer separates the fin-shaped gate from the source and from the drain, and a fourth portion of the insulation layer is located on a surface of the fin-shaped gate facing away from the active portion. Here, the insulation layer is integrally formed.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 29, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Hsin Chiao, Wei-Tsung Chen
  • Publication number: 20200343385
    Abstract: A memory structure includes a substrate, a gate electrode, a first isolation layer, a thin metal layer, indium gallium zinc oxide (IGZO) particles, a second isolation layer, an IGZO channel layer, and a source/drain electrode. The gate electrode is located on the substrate. The first isolation layer is located on the gate electrode. The thin metal layer is located on the first isolation layer, and has metal particles. The IGZO particles are located on the metal particles. The second isolation layer is located on the IGZO particles. The IGZO channel layer is located on the second isolation layer. The source/drain electrode is located on the IGZO channel layer.
    Type: Application
    Filed: April 12, 2020
    Publication date: October 29, 2020
    Inventors: Hsiao-Wen ZAN, Chuang-Chuang TSAI, Ching-Fu LIN, Zong-Xuan LI, Wei-Tsung CHEN
  • Publication number: 20200300976
    Abstract: A proximity sensor includes a substrate, a light source, a finger electrode, an active layer, and a transparent electrode layer. The substrate has opposite top and bottom surfaces. The light source faces toward the bottom surface of the substrate. The finger electrode is located on the top surface of the substrate, and has finger portions and gaps between every two adjacent finger portions. The active layer covers the finger electrode, and is located in the gaps. The transparent electrode layer is located on the active layer. When the light source emits light, the light through the gaps sequentially passes through the active layer and the transparent electrode layer onto a reflective surface. The light is reflected by the reflective surface to form reflected light, and the reflected light passes through the transparent electrode layer and is received by the active layer.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 24, 2020
    Inventors: Hsiao-Wen ZAN, Chuang-Chuang TSAI, Ching-Fu LIN, Chao-Hsuan CHEN, Zong-Xuan LI, Wei-Tsung CHEN
  • Patent number: 10672623
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 2, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Patent number: 10515596
    Abstract: A display apparatus is provided. Conducting states of switches in a pixel are switched to change charges stored in electrical energy storage cells that are connected to the switches, so as to provide a multi-stage driving voltage to a pixel electrode without increasing the manufacturing cost and circuit area of the display apparatus.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: December 24, 2019
    Assignee: E Ink Holdings Inc.
    Inventor: Wei-Tsung Chen
  • Publication number: 20190362685
    Abstract: A display device and a display driving circuit with electromagnetic interference suppression capability are provided. The display device includes a substrate, an active matrix, a display driver and a thin-film transistor (TFT) conditioning circuit. The active matrix disposed on the substrate includes multiple data lines, multiple gate lines and multiple pixels. The data lines intersect with the gate lines. The pixels are coupled to intersections of the data lines and the gate lines. The display driver disposed on the substrate generates signals for driving the data lines and/or the gate lines in response to a conditioned serial data clock. The TFT conditioning circuit disposed on the substrate is coupled to the display driver. The TFT conditioning circuit includes one or more TFTs, and attenuates an amplitude of a serial data clock in response to a predetermined gate bias to provide the conditioned serial data clock to the display driver.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Xue-Hung TSAI, Wei-Tsung CHEN, Yu-Lin WANG, Po-Hsin LIN
  • Patent number: 10339847
    Abstract: A display apparatus including a display panel and a driver circuit is provided. The display panel includes a display region and a non-display region. The non-display region includes a plurality of dummy pixels connected to one another. The driver circuit provides gate driving voltages and a test data voltage, so as to make the dummy pixels connected to one another generate a charging rate test signal in response to the test data voltage.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: July 2, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Wen-Yu Kuo, Guan-Ru Huang, Pei-Lin Huang, Wei-Tsung Chen
  • Patent number: 10326088
    Abstract: An organic thin film transistor includes a substrate, a hydrophobic layer, an oxide layer, a hydrophilic layer, a semiconductor layer, and a source/drain layer. The hydrophobic layer covers a surface of the substrate. The oxide layer is located on the hydrophobic layer and has plural segments. The hydrophilic layer is located on the segments of the oxide layer, and the oxide layer is located between the hydrophilic layer and the hydrophobic layer. The semiconductor layer is located on the hydrophilic layer, and the hydrophilic layer is located between the semiconductor layer and the oxide layer. The source/drain layer connects across the semiconductor layer on the segments of the oxide layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 18, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chun-Chih Chen, Hung-Chuan Liu, Zong-Xuan Li, Wei-Tsung Chen
  • Publication number: 20190122628
    Abstract: A driving substrate includes a substrate, at least one active device, a resistor, a first passivation layer and a second passivation layer. The active device including an oxide semiconductor layer and the resistor coupled to the active device are disposed on the substrate. The first passivation layer covers the active device, wherein a portion of the first passivation layer directly contacts to the oxide semiconductor layer such that the oxide semiconductor layer has a first conductivity. The second passivation layer covers the first passivation layer and the resistor, wherein a portion of the second passivation layer directly contacts to the resistor such that the resistor has a second conductivity. The first conductivity is different from the second conductivity.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 25, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20190115227
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Wei-Tsung CHEN, Po-Hsin LIN, Xue-Hung TSAI
  • Publication number: 20190079040
    Abstract: A sensing element includes a conductive substrate, a zinc oxide seed layer, a plurality of zinc oxide nanorods, a film with an electrical double layer, and an organic sensing layer. The zinc oxide seed layer is located on the conductive substrate. The zinc oxide nanorods extend from the zinc oxide seed layer. The film with the electrical double layer covers the zinc oxide nanorods. The organic sensing layer is located on the film with the electrical double layer.
    Type: Application
    Filed: August 22, 2018
    Publication date: March 14, 2019
    Inventors: Hsiao-Wen ZAN, Chuang-Chuang TSAI, Yu-Nung MAO, Hung-Chuan LIU, Zong-Xuan LI, Wei-Tsung CHEN