Abstract: A thin-film piezoelectric-material element includes a laminated structure part having a lower electrode film, a piezoelectric-material film laminated on the lower electrode film and an upper electrode film laminated on the piezoelectric-material film, a lower piezoelectric-material protective-film being formed with alloy material, and an upper piezoelectric-material protective-film being formed with alloy material. The piezoelectric-material film includes a size larger than the upper electrode film, a riser end-surface and step-surface formed on a top-surface of the upper electrode film side. The riser end-surface connects smoothly with a peripheral end-surface of the upper electrode film and vertically intersects with the top-surface. The step-surface intersects vertically with the riser end-surface. The lower piezoelectric-material protective-film, and the upper piezoelectric-material protective-film are formed with alloy material including Fe as main ingredient and having Co and Mo, by Ion beam deposition.

Abstract: A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.

Abstract: A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.

Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

Abstract: An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.

Abstract: A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.

Abstract: A two-photon-polymerization laser direct writing system based on an acousto-optic deflector is provided, which includes an ultrafast laser device, a beam expander, a scanning field center angular dispersion compensator, a two-dimensional acousto-optic deflector, a scanning field edge angular dispersion compensator, an astigmatism compensator and a focusing objective lens, the ultrafast laser device is configured to emit an ultrafast laser; the scanning field center angular dispersion compensator is configured to conduct precompensation on an angular dispersion at a center of a scanning field; the two-dimensional acousto-optic deflector is configured to deflect the ultrafast laser on the angular dispersion at the center of the scanning field; the scanning field edge angular dispersion compensator is configured to compensate for an angular dispersion at an edge of the scanning field; the astigmatism compensator is configured to compensate for astigmatism; the focusing objective lens is configured to conduct tig

Abstract: An image processing method includes: obtaining an original image; running an image processing model to perform moiré pattern removal processing on the original image to obtain a target image, the image processing model being a network model trained according to a moiré pattern training data set, and the image processing model including a multi-band module, the multi-band module being configured to process the original image to obtain an N-layer Laplacian pyramid of the original image, and obtain a first processing result feature map based on feature maps corresponding to N spatial frequency bands of the N-layer Laplacian pyramid, the target image being obtained according to the first processing result feature map, and N being a positive integer greater than or equal to 2.

Abstract: A power converter and method for improving the current control stability of power converter by balancing the secondary winding currents is provided herein. The power converter includes a primary circuit having switches controllably driven at an operating frequency to produce an AC output through a primary transformer winding, and a secondary circuit having first and second secondary windings having respective leakage inductances. The secondary circuit provides power at an output node based on a power transfer between the primary winding and the first and second secondary windings. At least one balance inductor is coupled in series with the first and second secondary windings, and configured to reduce a difference between the first leakage inductance and the second leakage inductance. The at least one balance inductor may further be configured to reduce a difference between first and second AC current peaks associated with the first and second secondary windings, respectively.

Abstract: An optical fiber sub-assembly and an optical fiber connector, where the optical fiber sub-assembly includes a connector component, where a first end of the connector component is used to connect an optical cable, and where a ferrule is disposed at a second end of the connector component. Additionally, a protection tube is disposed around the ferrule, where an end surface of the ferrule protrudes from an end surface of the protection tube or an end surface of the ferrule is level with an end surface of the protection tube. Further, the protection tube has a notch, and a beveled edge is formed at an outer end of the notch.

Abstract: A differential multiplier-accumulator accepts A and B digital inputs plus a sign bit and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. One of the positive and negative unit element is enabled by the sign bit, the enabled unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element, which charge to charge transfer lines, and the charge transfer lines are coupled to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product.

Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

Abstract: A plurality of unit elements share a charge transfer bus, each unit element accepts A and B digital inputs and generates a product P as an analog charge transferred to the charge transfer bus, each unit element comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates of each unit element are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges contributed by all unit elements to the charge transfer lines according to a bit weight and converted to a digital value output.

Abstract: A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.

Abstract: This disclosure relates to method and system for visual inspection of rotating components. The method includes representing rotation cycles of a rotating component as spatial features based on video or image frames, ascertaining and/or evolving Hidden Markov Model (HMM) chains for the cycles, ascertaining a count of the rotating component in the frames and/or labelling the frames with ascertained states of the HMM chains.

Abstract: Systems, methods, and computer-readable storage devices are disclosed for generating smart notes for a meeting based on participant actions and machine learning. One method including: receiving meeting data from a plurality of participant devices participating in an online meeting; continuously generating text data based on the received audio data from each participant device of the plurality of participant devices; iteratively performing the following steps until receiving meeting data for the meeting has ended, the steps including: receiving an indication that a predefined action has occurred on the first participating device; generating a participant segment of the meeting data for at least the first participant device from a first predetermined time before when the predefined action occurred to when the predefined action occurred; determining whether the receiving meeting data of the meeting has ended; and generating a summary of the meeting.

Abstract: A thin-film piezoelectric material elements are arranged on a thin-film piezoelectric material substrate. The thin-film piezoelectric material substrate includes an insulator on Si substrate including a substrate including silicon and an insulating layer on a surface of the substrate. The thin-film piezoelectric material element includes a thin-film laminated part on a top surface of the insulating layer. The thin-film laminated part includes a YZ seed layer including yttrium and zirconium, and formed on the top surface; a lower electrode film laminated on the YZ seed layer; a piezoelectric material film including lead zirconate titanate, shown by a formula Pb (ZrxTi(1-x)) O3(0?×?1), and an upper electrode film laminated on the piezoelectric material film. The thin-film laminated part further includes an upper piezoelectric-material protective-film, laminated on the upper side of the upper electrode film.

Abstract: Techniques for prioritization of data streams include transmitting a plurality of data streams to a first device over a network where each data stream is configured to cause the first device to perform a specific function, dynamically detecting a bandwidth limitation limiting an amount of available bandwidth for transmitting the plurality of data streams, dynamically determining bandwidth reduction criteria by identifying a first subset of the plurality of data streams to stop transmitting based on the specific function that each respective data stream causes the first device to perform, temporarily stopping transmitting of the first subset of data streams configured to cause the first device to perform a first set of functions, and continuing to transmit a second subset of data streams not included in the first subset of the data streams to the first device to cause the first device to continue to perform a second set of functions.

Abstract: One example optical splitter chip includes a substrate. The substrate is configured with an input port, configured to receive first signal light, an uneven optical splitting unit, configured to split the first signal light into at least second signal light and third signal light, where optical power of the second signal light is different from optical power of the third signal light, a first output port, configured to output the second signal light, an even optical splitting unit group, including at least one even optical splitting unit, configured to split the third signal light into at least two channels of equal signal light, where optical power of the at least two channels of equal signal light is the same, and at least two second output ports, which are in a one-to-one correspondence with the at least two channels of equal signal light.