Patents by Inventor Wei Yang

Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Publication number: 20240112735
    Abstract: In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Wei Cao, Jiacen Guo
  • Publication number: 20240113203
    Abstract: A method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. A first spacer layer is deposited over the gate and over the fin in a source/drain region. The first spacer layer has a first etch rate. A second spacer layer is deposited over the first spacer layer. The second spacer layer has a second etch rate less than the first etch rate. The plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. After forming the trench, inner spacers are formed along a sidewall surface of the trench. In various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.
    Type: Application
    Filed: January 25, 2023
    Publication date: April 4, 2024
    Inventors: Che-Lun CHANG, Wei-Yang LEE, Chia-Pin LIN
  • Publication number: 20240114758
    Abstract: A metal mask has a first surface, a second surface opposite to the first surface, first and second openings provided on the first and second surfaces respectively, and first and second through holes communicating with the first and second openings respectively. The juncture of the first and second through holes further has an annular protrusion. The mask satisfies the in equations: 1 ? ?m 2 < 1 2 × W × H < 15 ? ?m 2 ? and ? 30 ? ° < ? < 65 ? ° , wherein W is the horizontal distance between an edge of the first opening and an imaginary connecting line passing through an edge of the second opening and an end edge of the annular protrusion, H is the vertical distance between the end edge of the annular protrusion and the first surface, and ? is the included angle between the imaginary connecting line and an imaginary extending plane of the first surface. The metal mask is effective in reducing shadow effect, thereby improving evaporation quality.
    Type: Application
    Filed: November 15, 2022
    Publication date: April 4, 2024
    Inventors: Yun-Pei YANG, Chi-Wei LIN
  • Publication number: 20240107986
    Abstract: A fish identification method is provided. The fish identification method includes capturing an image through a processor, wherein the image includes a fish image. The fish identification method includes identifying a plurality of feature points of the fish image through a coordinate detection model and obtaining a plurality of sets of feature-point coordinates. Each of the plurality of sets of feature-point coordinates corresponds to each of the plurality of feature points. The fish identification method further includes calculating a body length or an overall length of the fish image according to the plurality of sets of feature-point coordinates of the image.
    Type: Application
    Filed: January 13, 2023
    Publication date: April 4, 2024
    Inventors: Zhe-Yu LIN, Chih-Yi CHIEN, Chen Wei YANG, Tsun-Hsien KUO
  • Publication number: 20240110465
    Abstract: A method for shale gas exploitation includes performing horizontal drilling operation on an area to be constructed, forming a crack around a horizontal drill hole wall by shaped charge perforation; expanding the crack around a horizontal hole hydraulic fracturing, and extracting methane gas after a fracturing fluid is discharged; after methane gas is reduced, performing in-situ combustion explosion fracturing on the methane involved in horizontal drilling; thereafter continuing to expand the crack in the horizontal drill hole such that methane continues to seep out, and continuing extracting methane; repeating combustion explosion fracturing and extraction operations, so as to increase combustion explosion cracking permeability, and greatly enhance the exploitation effect of shale gas. The method is suitable for fracturing reconstruction of unconventional oil and gas reservoirs such as shale gas reservoirs, coal seam gas reservoirs and tight sandstone gas reservoirs.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 4, 2024
    Inventors: WEI YANG, ZENING WEI, CHENG ZHAI, Yihan WANG, WENYUAN WANG, WENXIAO ZHANG
  • Publication number: 20240113113
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20240110997
    Abstract: Disclosed are a device and method for detecting defects of a high-voltage cable cross-bonded grounding system. The method comprises: selecting a protective grounding box of a cross-bonded grounding system, respectively connecting a signal excitation coupler to A-phase, B-phase and C-phase coaxial cables of the protective grounding box, selecting a stable signal with a frequency different from a power frequency or a field interference frequency, and testing effective current values and phases responded by the A-phase, B-phase and C-phase coaxial cables when the stable signal with the frequency F1 is injected into the A-phase, B-phase and C-phase coaxial cables of the protective grounding box in a coupled manner; and obtaining resistances and inductances of branch circuits of the cable cross-bonded grounding system by calculation according to measurement data, and determining if the cable cross-bonded grounding system has a connection defect.
    Type: Application
    Filed: August 4, 2022
    Publication date: April 4, 2024
    Applicants: STATE GRID JIANGSU ELECTRIC POWER CO., LTD. RESEARCH INSTITUTE, STATE GRID JIANGSU ELECTRIC POWER CO., LTD., JIANGSU ELECTRIC POWER RESEARCH INSTITUTE CO., LTD.
    Inventors: Jingying CAO, Qiang HUANG, Jinggang YANG, Jie CHEN, Rong SUN, Jianjun LIU, Xiao TAN, Libin HU, Chenying LI, Wei ZHANG
  • Publication number: 20240112360
    Abstract: A measurement system includes a camera and a processor. The camera is configured to capture a measurement card image of a measurement card, and the measurement card image includes a number of feature pattern images. The processor is electrically connected to the camera and configured for analyzing the feature pattern images to obtain a feature point coordinate of a feature point of each feature pattern image, and inputting the feature point coordinates into a conversion matrix to obtain a tip coordinate of a tip of the measurement card.
    Type: Application
    Filed: January 18, 2023
    Publication date: April 4, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Wei CHANG, Shih-Fang YANG MAO, Tien-Yan MA
  • Publication number: 20240113201
    Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.
    Type: Application
    Filed: January 25, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Ching WANG, Wei-Yang LEE, Bo-Yu LAI, Chung-I YANG, Sung-En LIN
  • Publication number: 20240114449
    Abstract: A network node may transmit a first signal to a first radio at a user equipment (UE). The UE may receive the first signal from the network node. The first signal may include a first configuration for a second radio at the UE. The UE may operate the second radio in a first mode based on the first configuration received via the first radio. The first radio may have a lower power consumption than the second radio or the second radio may have the lower power consumption than the first radio. For example, one radio may be a low-power wake-up radio (LP-WUR) having a lower power consumption than a main radio (MR) at the UE. The network node and the UE may communicate with one another via the second radio at the UE based on the first configuration transmitted to the first radio.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Ahmed ELSHAFIE, Hung Dinh LY, Huilin XU, Wanshi CHEN, Changhwan PARK, Linhai HE, Yuchul KIM, Wei YANG, Peter GAAL, Le LIU, Diana MAAMARI
  • Publication number: 20240114476
    Abstract: Apparatuses, systems, and methods for synchronization and resource allocation for sidelink positioning, e.g., in 5G NR systems and beyond. A device, e.g., a UE or an LMF, may be configured to transmit, to a plurality of wireless devices, an anchor selection request for a sidelink positioning procedure for a target UE. The device may be configured to receive, from one or more wireless devices of the plurality of wireless devices, an anchor selection response. The device may be configured to select based, at least in part, on the anchor selection responses, one or more anchor devices from the one or more wireless devices.
    Type: Application
    Filed: August 17, 2023
    Publication date: April 4, 2024
    Inventors: Oghenekome Oteri, Sigen Ye, Dawei Zhang, Wei Zeng, Chunxuan Ye, Weidong Yang, Haitong Sun, Seyed Ali Akbar Fakoorian
  • Publication number: 20240112373
    Abstract: A point cloud encoding processing method includes obtaining a current to-be-encoded node in a target queue, where the target queue includes an occupied node in a space block corresponding to a constructed tree structure based on first geometric information, the first geometric information is obtained by preprocessing based on geometric information of a to-be-encoded N-th frame point cloud, and N is an integer greater than 1; and determining an encoding mode of the current to-be-encoded node based on whether the current to-be-encoded node meets an encoding condition of an isolated point. The encoding condition of the isolated point includes an occupancy status of a target node meets a preset condition. The target node is a node that is in encoded nodes and that is associated with the current to-be-encoded node.
    Type: Application
    Filed: November 29, 2023
    Publication date: April 4, 2024
    Inventors: Wei Zhang, Jiaming Nie, Zhuoyi Lv, Fuzheng Yang
  • Publication number: 20240113214
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first channel member suspended over a substrate and a second channel member suspended over the first channel member and spaced apart from the first channel member along a first direction. The semiconductor structure also includes a gate structure wrapping around the first channel member and the second channel member and a dielectric structure encircled by the first channel member, the second channel member, the gate structure, and the source/drain structure. In addition, the dielectric structure includes a porous material or an air gap. The semiconductor structure also includes a first epitaxial layer attached to the first channel member, and the first epitaxial layer has a first extending portion protruding from a bottom surface of the first channel member along the first direction and extending into the dielectric structure.
    Type: Application
    Filed: March 3, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Lun Chang, Kuan-Ting Pan, Wei-Yang Lee
  • Publication number: 20240112300
    Abstract: The present invention discloses a method and an apparatus for 2D regularized planar projection of a point cloud. The method includes: obtaining original point cloud data; initializing a planar structure of 2D projection of the point cloud; calculating horizontal azimuth information of the point cloud based on the original point cloud data; and determining a mapping relationship between the original point cloud data and the planar structure of 2D projection based on the horizontal azimuth information, to obtain a planar structure of 2D regularized projection of the point cloud. In the present invention, a large-scale point cloud may be projected to a 2D regularized planar structure without 2D local search. Therefore, complexity of an algorithm can be reduced, time spent on 2D regularized planar projection of the point cloud can be reduced, and algorithm performance can be improved.
    Type: Application
    Filed: May 18, 2022
    Publication date: April 4, 2024
    Inventors: Wei ZHANG, Fuzheng YANG, Yuxin DU, Jiarun Song
  • Publication number: 20240113841
    Abstract: A user equipment (UE) includes a transceiver and a processor configured to receive, from a network via the transceiver, a configuration of channel state information (CSI) report characteristics. The CSI report characteristics include one or more of: a maximum size of a CSI report payload, a maximum number of bits per layer or rank, a neural network (NN) identification (ID), or an expected CSI report content type. The processor is configured to generate a CSI report, in accordance with the received CSI report characteristics, to transmit to the network via the transceiver.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Huaning Niu, Weidong Yang, Chunxuan Ye, Dawei Zhang, Wei Zeng, Oghenekome Oteri, Ankit Bhamri, Hong He
  • Publication number: 20240113429
    Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.
    Type: Application
    Filed: August 16, 2023
    Publication date: April 4, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Sheng-Chin Hsu, Chia-Hung Chen, Chih-Wei Liao, Hau Yuen Tan, Hao-Hsiang Yang, Shih-Keng Huang
  • Publication number: 20240112744
    Abstract: The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Wei Cao, Deepanshu Dutta
  • Patent number: 11948489
    Abstract: A display panel, a display device and a driving method. The display panel includes a display region and a peripheral region. The display region includes a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region includes a gate drive circuit. The display region further includes a plurality of gate lines and a plurality of data lines. The gate drive circuit comprises a plurality of shift register units, and the plurality of gate lines are electrically connected with the plurality of shift register units. The gate drive circuit comprises two shift-register-unit scanning groups, in the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit form one shift register unit group.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 2, 2024
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhaohui Meng, Wei Sun, Wenchao Han, Hong Yang, Lin Cong, Wenjun Xiao
  • Patent number: 11949001
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu