Abstract: A display device is provided. The display device has a display side and includes: a first substrate, a flexible film, and a first adhesive material. The first substrate has a first surface, a second surface, and a side surface. The first surface is closer to the display side than the second surface. The side surface includes a first portion, a second portion, and a third portion. The second portion is located between the first portion and the third portion. In a cross-section view, a first included angle is formed between the first portion and an extension line of the first surface, and a second included angle is formed between the third portion and an extension line of the second surface. The flexible film is connected to the first substrate. The first adhesive material contacts at least a portion of the flexible film.

Abstract: Method and UE are provided for determining precoder of MIMO system. In particular, a BS can transmit at least one CSI-RS to the UE. The UE can receive the at least one CSI-RS, and estimate at least one covariance matrix of at least one downlink channel matrix according to the at least one CSI-RS at different times and frequencies. Then, the UE can transmit the at least one covariance matrix or at least one parameter associated with the least one covariance matrix to the BS for the BS to reconstruct at least one covariance matrix, and determine a precoder according to the at least one reconstructed covariance matrix.

Abstract: A single image deraining method is proposed. A wavelet transforming step processes an initial rain image to generate an i-th stage low-frequency rain image and a plurality of i-th stage high-frequency rain images. An image deraining step inputs the i-th stage low-frequency rain image to a low-frequency deraining model to output an i-th stage low-frequency derain image. A first inverse wavelet transforming step recombines the n-th stage low-frequency derain image with the n-th stage high-frequency derain images to form an n-th stage derain image. A weighted blending step blends a (n?1)-th stage low-frequency derain image with the n-th stage derain image to generate a (n?1)-th stage blended derain image. A second inverse wavelet transforming step recombines the (n?1)-th stage high-frequency derain images with the (n?1)-th stage blended derain image to form a (n?1)-th stage derain image, and sets n to n?1 and repeats the last two steps.

Abstract: A display panel and a display apparatus are disclosed. The display apparatus includes the display panel and a sensing device. The display panel includes a substrate, a first signal line, and a first dummy conductive pattern. The substrate includes a functional display region, a buffer region, and a general display region. The buffer region is located between the functional display region and the general display region. The first signal line and the first dummy conductive pattern are disposed on the substrate and correspond to the buffer region. The first dummy conductive pattern is overlapped with a part of the first signal line. The sensing device is overlapped with the functional display region.

Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.

Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 ?m; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 ?m.

Abstract: An integrated circuit (IC) with a semiconductor device and an interconnect structure with carbon layers and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a source/drain region on the fin structure, forming a contact structure on the S/D region, forming an oxide layer on the contact structure, forming a conductive carbon line within a first insulating carbon layer on the oxide layer, forming a second insulating carbon layer on the first insulating carbon layer, and forming a via within the second insulating carbon layer.

Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

Abstract: A dark fiber dense wavelength division multiplexing service path design microservice (ddSPDmS) can provide a scalable self-contained meta-data driven approach for a flexible implementation of a dark fiber dense wavelength division multiplexing (DWDM) service path design solution. The service plan design solution can be used as a standalone solution or integrated with a network management application. In order to manage a large volume of circuit designs, multiple microservices can accept application program interface (API) requests in a cloud environment. Permission can then be given to any application to use the API to make a call to the design and inventory. Additionally, metadata templates can be designed to support a node, a link, and/or a topology for the microservices.

Abstract: A display device is provided. The display device has a display side and includes: a first substrate and a second substrate. The first substrate has a first surface and a second surface, wherein the first surface is closer to the display side than the second surface. The second substrate is disposed opposite the first substrate. The second surface is located between the first surface and the second substrate, and the area of the first substrate is greater than the area of the second substrate in a top view direction. The first substrate has a side surface, and the side surface includes a chamfered structure.

Abstract: An eye center localization method includes performing an image sketching step, a frontal face generating step, an eye center marking step and a geometric transforming step. The image sketching step is performed to drive a processing unit to sketch a face image from the image. The frontal face generating step is performed to drive the processing unit to transform the face image into a frontal face image according to a frontal face generating model. The eye center marking step is performed to drive the processing unit to mark a frontal eye center position information on the frontal face image. The geometric transforming step is performed to drive the processing unit to calculate two rotating variables between the face image and the frontal face image, and calculate the eye center position information according to the two rotating variables and the frontal eye center position information.

Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

Abstract: The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.

Abstract: The present disclosure provides source/drain epitaxial structures and source/drain contacts wrapped with graphene layers in fin structures of FETs, and fabricating methods thereof. In some embodiments, a disclosed semiconductor device includes a fin structure on a substrate. The fin structure includes an epitaxial region. The semiconductor device further includes a metal contact above the epitaxial region, and a graphene film covering a top surface and sidewalls of the epitaxial region and covering a bottom surface and sidewalls of the metal contact.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A method for generating a movement path of a tool configured to utilize a virtual path to generate a correct path that fits an allowable error is provided. The method includes a receiving step implemented by receiving the virtual path and a precision data; an auxiliary point establishing step implemented by adding a plurality of auxiliary points in a plurality of arc sections; a moving and detecting step implemented by controlling the tool to sequentially move to a plurality of predetermined points and the auxiliary points according to the virtual path; and a calculating step implemented by amending the predetermined points or the auxiliary points in the virtual path if a difference between a real-time position coordinate and corresponding one of the predetermined points or the auxiliary points is greater than the allowable error to generate the correct path.

Abstract: An AI process flow management system and method for automatic visual inspection are introduced, allowing an edge computing apparatus to exchange data with an AI cloud apparatus through a network, and allowing the AI cloud apparatus to perform training and provide a report to the edge computing apparatus. During execution of the edge computing apparatus and AI cloud apparatus in a training stage, the AI cloud apparatus fetches image information, generates label information according to the image information, creates a training model according to the label information, updates the training model, and allows the updated training model to be downloaded by the edge computing apparatus. The training stage is restarted in real time through AI technology, and the training model is created and updated in real time through the label information, thereby enhancing visual inspection efficiency.

Abstract: A method for manufacturing a conductive laminate and a conductive laminate are provided. The method for manufacturing the conductive laminate includes steps of: providing a substrate having a surface; immersing the substrate into a modifying solution including a silane with a hydrophilic group to form a discontinuous modified layer on the surface of the substrate; forming a barrier layer on the surface of the substrate and the discontinuous modified layer, and forming a conductive layer on a surface of the barrier layer. The barrier layer includes a polymer, and the polymer is selected from the group consisting of: polyvinyl alcohol, polyvinylpyrrolidone, polyacrylic acid, polyethylene glycol, and any combination thereof.

Abstract: A display device includes a first pixel region and a second pixel region adjacent to the first pixel region. The display device includes: a first substrate; a second substrate opposite to the first substrate; and a plurality of spacers disposed between the first substrate and the second substrate. Herein, a first portion of the plurality of spacers are disposed in the first pixel region, a second portion of the plurality of spacers are disposed in the second pixel region, a disposition density of the second portion of the plurality of spacers in the second pixel region is different from a disposition density of the first portion of the plurality of spacers in the first pixel region.

Abstract: Provided are an adhesion promoting layer, a method for depositing a conductive layer on an inorganic or organic-inorganic hybrid substrate and a conductive structure. The adhesion promoting layer is suitable for depositing a conductive layer on an inorganic or organic-inorganic hybrid substrate, which includes a metal oxide layer and an interface layer. The metal oxide layer is disposed on the inorganic or organic-inorganic hybrid substrate. The interface layer is disposed between the metal oxide layer and the inorganic or organic-inorganic hybrid substrate. The metal oxide layer includes metal oxide and a chelating agent. The interface layer includes the metal oxide, the chelating agent and metal-nonmetal-oxide composite material.