Patents by Inventor Weidong Tian

Weidong Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130065374
    Abstract: A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.
    Type: Application
    Filed: April 19, 2012
    Publication date: March 14, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Weidong Tian, Ming-Yeh Chuang, Rajni J. Aggarwal
  • Patent number: 8373215
    Abstract: A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: February 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Weidong Tian, Imran Khan
  • Publication number: 20120292682
    Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shanjen Pan, Allan T. Mitchell, Weidong Tian
  • Publication number: 20120098045
    Abstract: A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 26, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Weidong Tian, Imran Khan
  • Patent number: 8110414
    Abstract: A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ?100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Marshall O. Cathey, Jr., Pushpa Mahalingam, Weidong Tian, David C. Guiling, Xinfen Chen, Binghua Hu, Sopa Chevacharoenkul
  • Publication number: 20100276783
    Abstract: A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ?100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Applicant: TEXAS INSTRUMENTS INC
    Inventors: MARSHALL O. CATHEY, PUSHPA MAHALINGAM, WEIDONG TIAN, DAVID C. GUILING, XINFEN CHEN, BINGHUA HU, SOPA CHEVACHAROENKUL
  • Patent number: 7671445
    Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: March 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Weidong Tian, Bradley Sucher, Zafar Imam
  • Patent number: 7592252
    Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: September 22, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Weidong Tian, Bradley Sucher, Zafar Imam
  • Patent number: 7498219
    Abstract: Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through implantation of other techniques to reduce the voltage coefficient of capacitance and/or the dielectric absorption of the capacitor.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: March 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Weidong Tian, Jozef Mitros, Victor Ivanov
  • Publication number: 20080277761
    Abstract: An integrated circuit includes a substrate having a semiconducting surface, and at least one isolation capacitor on the surface. The capacitor includes a bottom electrically conductive plate in or on the surface, a multi-layer dielectric comprising stack over the bottom plate, and a top electrically conductive plate formed over the dielectric stack. The dielectric stack comprises at least one layer of silicon dioxide and at least one layer of silicon nitride, wherein the layer of silicon nitride is located immediately below or immediately above the top plate.
    Type: Application
    Filed: January 30, 2008
    Publication date: November 13, 2008
    Inventors: Pushpa Mahalingam, David C. Guiling, Sunny K. Lee, Ramon F. Figueroa, Weidong Tian, Yvonne D. Patton, Imran M. Khan
  • Publication number: 20080137262
    Abstract: One embodiment of the present invention relates to a capacitor. The capacitor includes a first electrode and a capacitor dielectric layer along-side the first capacitor electrode. A second electrode is found along-side the capacitor dielectric layer includes a number of inter-layers that are configured to prevent defects in the second capacitor electrode. Other methods and devices are also disclosed.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 12, 2008
    Inventors: Pushpa Mahalingam, Alexander Wong, Marshall O. Cathey, Weidong Tian, Yvonne Dianne Patton, Joseph William Palmer, Billy Alan Wofford
  • Publication number: 20070057247
    Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 15, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Weidong Tian, Bradley Sucher, Zafar Imam
  • Patent number: 7119444
    Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: October 10, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Weidong Tian, Bradley Sucher, Zafar Imam
  • Publication number: 20060214170
    Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.
    Type: Application
    Filed: May 30, 2006
    Publication date: September 28, 2006
    Inventors: Weidong Tian, Bradley Sucher, Zafar Imam
  • Patent number: 7045418
    Abstract: The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wherein the floating gate (230) has a metal control gate (250) located thereover. The semiconductor device (200), in the same embodiment, further includes a dielectric layer (240) located between the floating gate 230 and the metal control gate (250), the dielectric layer (240) having a gettering material located therein.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jozef Mitros, Weidong Tian, Pinghai Hao, Victor Ivanov
  • Publication number: 20060033173
    Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.
    Type: Application
    Filed: August 13, 2004
    Publication date: February 16, 2006
    Inventors: Weidong Tian, Bradley Sucher, Zafar Imam
  • Publication number: 20040209423
    Abstract: Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through implantation of other techniques to reduce the voltage coefficient of capacitance and/or the dielectric absorption of the capacitor.
    Type: Application
    Filed: April 15, 2003
    Publication date: October 21, 2004
    Inventors: Weidong Tian, Jozef Mitros, Victor Ivanov
  • Patent number: 6794700
    Abstract: The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the capacitor 300 includes a first conductive plate 320 located over a semiconductor substrate 310, wherein the first conductive plate 320 has a second conductive plate 340 located thereover. The capacitor 300, in the same embodiment, further includes a dielectric layer 330 located between the first conductive plate 320 and the second conductive plate 340, wherein the dielectric layer 330 includes a Group 17 element.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: September 21, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Eric Beach, Weidong Tian, Pinghai Hao
  • Publication number: 20040178438
    Abstract: The present invention provides a semiconductor device 200, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device 200 includes a floating gate 230 located over a semiconductor substrate 210, wherein the floating gate 230 has a metal control gate 250 located thereover. The semiconductor device 200, in the same embodiment, further includes a dielectric layer 240 located between the floating gate 230 and the metal control gate 250, the dielectric layer 240 having a gettering material located therein.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 16, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Jozef Mitros, Weidong Tian, Pinghai Hao, Victor Ivanov
  • Patent number: 6706635
    Abstract: The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: March 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Imran M. Khan, William E. Nehrer, James Todd, Weidong Tian, Louis N. Hutter