Patents by Inventor Weihua Tang

Weihua Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200219790
    Abstract: An integrated circuit assembly may be formed using a phase change material as an electromagnetic shield and as a heat dissipation mechanism for the integrated circuit assembly. In one embodiment, the integrated circuit assembly may comprise an integrated circuit package including a first substrate having a first surface and an opposing second surface, and at least one integrated circuit device having a first surface and an opposing second surface, wherein the at least one integrated circuit device is electrically attached by the first surface thereof to the first surface of the first substrate; and a phase change material formed on the integrated circuit package.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 9, 2020
    Applicant: INTEL CORPORATION
    Inventors: Aastha Uppal, Je-Young Chang, Weihua Tang, Minseok Ha
  • Publication number: 20200111720
    Abstract: An Integrated Circuit (IC) device structure is provided. The IC device structure includes a first substrate, first one or more dies coupled to a first side of the first substrate by a first plurality of interconnect structures, second one or more dies coupled to a first section of a second side of the substrate by a second plurality of interconnect structures, and a third plurality of interconnect structures to couple a second section of the second side of the substrate to a second substrate. In an example, at least a part of the second one or more dies are within a cavity in the second substrate.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: Zhimin Wan, Shankar Devasenathipathy, Chia-Pin Chiu, Chandra Mohan Jha, Weihua Tang
  • Publication number: 20200105643
    Abstract: An integrated heat spreader includes channel structures assembled in a frame. Each channel structure is independent of the other, and can be used to dissipate heat from integrated circuitry at a specific location within a package, and without allowing heat from that particular location to propagate to integrated circuitry at other locations within the package. Each channel structure can be implemented with metal having a high thermal conductivity (e.g., copper). The channel structures can be used in conjunction with liquid-based cooling or air-based cooling. The frame can be implemented with low thermal conductivity molding compound or plastic so the heat transfer from one channel structure to another is inhibited. The channel structures can have different configurations (e.g., straight, pillars, and/or pin fins) to provide different rates of flow, mixing, and/or cooling. The flow direction of air or liquid for the channel structures can be the same (parallel) or different (counter).
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: ZHIMIN WAN, CHIA-PIN CHIU, CHANDRA MOHAN JHA, WEIHUA TANG, SHANKAR DEVASENATHIPATHY
  • Publication number: 20200105639
    Abstract: Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Krishna Vasanth Valavala, Ravindranath Mahajan, Chandra Mohan Jha, Kelly Lofgreen, Weihua Tang
  • Publication number: 20200098666
    Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: INTEL CORPORATION
    Inventors: ZHIMIN WAN, CHIA-PIN CHIU, POOYA TADAYON, JOE F. WALCZYK, CHANDRA MOHAN JHA, WEIHUA TANG, SHRENIK KOTHARI, SHANKAR DEVASENATHIPATHY
  • Patent number: 9608844
    Abstract: Embodiments of systems and methods for performing channel estimation on Orthogonal frequency-division multiplexing (OFDM) signals are described. In one embodiment, a method for performing channel estimation on an OFDM signal involves performing blind channel phase estimation on an OFDM signal to obtain channel phase information and performing blind channel magnitude estimation on the OFDM signal to obtain channel magnitude information. Each of performing blind channel phase estimation on the OFDM signal and performing blind channel magnitude estimation on the OFDM signal involves detecting and suppressing a signal path of the OFDM signal. Other embodiments are also described.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 28, 2017
    Assignee: NXP B.V.
    Inventors: Weihua Tang, Semih Serbetli
  • Publication number: 20160377658
    Abstract: Improved fluid flow is described for a temperature control actuator that is used in semiconductor device test. In one example, the apparatus includes a top plate configured to thermally connect to a semiconductor device under test, a channel plate thermally connected to the top plate and having a plurality of fluid channels to receive a thermally controlled fluid from an inlet to exchange heat with the thermally controlled fluid in the channel and to eliminate the thermally controlled fluid to an outlet, a manifold to provide the thermally controlled fluid to the inlet and to receive the thermally controlled fluid through the outlet, and a flow guide in the channel thermally connected to the top plate.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: Paul J. DIGLIO, John C. JOHNSON, Weihua TANG
  • Publication number: 20150349981
    Abstract: Embodiments of systems and methods for performing channel estimation on Orthogonal frequency-division multiplexing (OFDM) signals are described. In one embodiment, a method for performing channel estimation on an OFDM signal involves performing blind channel phase estimation on an OFDM signal to obtain channel phase information and performing blind channel magnitude estimation on the OFDM signal to obtain channel magnitude information. Each of performing blind channel phase estimation on the OFDM signal and performing blind channel magnitude estimation on the OFDM signal involves detecting and suppressing a signal path of the OFDM signal. Other embodiments are also described.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 3, 2015
    Applicant: NXP B.V.
    Inventors: Weihua Tang, Semih Serbetli
  • Patent number: 9071492
    Abstract: A first error-correcting decoder, adapted to decode the data bits of a received OFDM symbol; a re-encoder, to receive decoded bits and adapted to re-encode a leading portion of the decoded bits; a mapper, to receive the re-encoded leading portion of bits, map these bits to a corresponding subset of the plurality of sub-carriers, and thereby estimate a modulation symbol that was applied to each sub-carrier of said subset a channel estimator, to produce a channel estimate by comparing the sub-carrier modulation symbols with the corresponding sub-carriers actually received by the receiver; and an equalizer, to process the received signal to remove distortions introduced by the transmission channel, using the channel estimate, the re-encoder is adapted to begin re-encoding the leading portion of the bits before a trailing portion of the bits has been decoded by the decoder.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: June 30, 2015
    Assignee: NXP, B.V.
    Inventors: Weihua Tang, Arie Geert Cornelis Koppelaar
  • Publication number: 20150060527
    Abstract: Embodiments of a method for performing a thermal compression bonding process with a non-uniform temperature pattern and a heater having the non-uniform temperature pattern are disclosed. In some embodiments, the heater includes a plurality of heating element segments configured to generate the non-uniform temperature pattern. The configuration comprises a plurality of heating element segment densities or a plurality of heating element segment resistances.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Inventors: Weihua Tang, Sung-Won Moon, Sangil Lee
  • Publication number: 20150001736
    Abstract: Die connections are described using different underfill types for different regions. In one example, a first electrically-non-conductive underfill paste (NCP) type is applied to an I/O region of a first die. A second NCP type is applied outside the I/O region of the first die, the second NCP type having more filler than the first NCP type, and the second die is bonded to a first die using the NCP.
    Type: Application
    Filed: June 29, 2013
    Publication date: January 1, 2015
    Inventors: Hualiang Shi, Shengquan Ou, Sairam Agraharam, Shan Zhong, Sivakumar Nagarajan, Weihua Tang
  • Patent number: 8920934
    Abstract: Hybrid solder for solder balls and filled paste are described. A solder ball may be formed of a droplet of higher temperature solder and a coating of lower temperature solder. This may be used with a solder paste that has an adhesive and a filler of low temperature solder particles, the filler comprising less than 80 weight percent of the paste. The solder balls and paste may be used in soldering packages for microelectronic devices. A package may be formed by applying a solder paste to a bond pad of a substrate, attaching a hybrid solder ball to each pad using the paste, and attaching the package substrate to a microelectronic substrate by reflowing the hybrid solder balls to form a hybrid solder interconnect.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Hongjin Jiang, Arun Kumar C. Nallani, Rajen S. Sidhu, Martha A. Dudek, Weihua Tang
  • Patent number: 8904266
    Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: December 2, 2014
    Assignee: NXP, B.V.
    Inventors: Weihua Tang, Nur Engin, Frits Anthonie Steenhof, Marc Klaassen, Andries Pieter Hekstra, Sergie Valerjewitsch Sawitzki
  • Publication number: 20140291843
    Abstract: Hybrid solder for solder balls and filled paste are described. A solder ball may be formed of a droplet of higher temperature solder and a coating of lower temperature solder. This may be used with a solder paste that has an adhesive and a filler of low temperature solder particles, the filler comprising less than 80 weight percent of the paste. The solder balls and paste may be used in soldering packages for microelectronic devices. A package may be formed by applying a solder paste to a bond pad of a substrate, attaching a hybrid solder ball to each pad using the paste, and attaching the package substrate to a microelectronic substrate by reflowing the hybrid solder balls to form a hybrid solder interconnect.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Inventors: Hongjin Jiang, Arun Kumar C. Nallani, Rajen S. Sidhu, Martha A. Dudek, Weihua Tang
  • Publication number: 20130279558
    Abstract: Receiving an OFDM signal having a series of OFDM symbols, each having sub-carriers, each modulated by at least one data bit encoded with error-correcting code. The receiver has a first error-correcting decoder to decode sequentially data bits of a received first OFDM symbol; a re-encoder to receive decoded bits and re-encode a leading portion of the decoded bits; a mapper to receive the re-encoded leading portion of bits, map these bits to a corresponding subset of the sub-carriers, and thereby estimate a modulation symbol applied to each sub-carrier, by the transmitter; a channel estimator to produce a channel estimate by comparing sub-carrier modulation symbols with corresponding sub-carriers received by the receiver; and an equalizer to process the received signal to remove distortions from the transmission channel, using the channel estimate. The re-encoder begins re-encoding the leading portion of the bits before a trailing portion has been decoded.
    Type: Application
    Filed: April 11, 2013
    Publication date: October 24, 2013
    Applicant: NXP B.V.
    Inventors: Weihua TANG, Arie Geert Cornelis KOPPELAAR
  • Patent number: 8566683
    Abstract: Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 22, 2013
    Assignee: NXP, B.V.
    Inventors: Andries Pieter Hekstra, Weihua Tang
  • Publication number: 20120042229
    Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.
    Type: Application
    Filed: August 10, 2010
    Publication date: February 16, 2012
    Applicant: NXP B.V.
    Inventors: Weihua Tang, Nur Engin, Frits Anthonie Steenhof, Marc Klaassen, Andries Pieter Hekstra, Sergei Valerjewitsch Sawitzki
  • Publication number: 20110161787
    Abstract: Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Applicant: NXP B.V.
    Inventors: Andries Pieter Hekstra, Weihua Tang