Patents by Inventor Weilun Hong
Weilun Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240105460Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
-
Patent number: 11854821Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: GrantFiled: April 1, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
-
Publication number: 20230377898Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventors: Wan-Chun Pan, William Weilun Hong, Ying-Tsung Chen
-
Publication number: 20230267264Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin-Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
-
Patent number: 11718812Abstract: A cleaning composition for cleaning a surface of a substrate comprising silicon germanium after a chemical mechanical polishing process is provided. The cleaning composition includes an oligomeric or polymeric polyamine, at least one wetting agent, a pH adjusting agent, and a solvent.Type: GrantFiled: March 3, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ji Cui, William Weilun Hong, Gin-Chen Huang, Shich-Chang Suen, Kei-Wei Chen
-
Publication number: 20230230846Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: ApplicationFiled: March 15, 2023Publication date: July 20, 2023Inventors: Yi-Sheng LIN, Chi-Jen LIU, Chi-Hsiang SHEN, Te-Ming KUNG, Chun-Wei HSU, Chia-Wei HO, Yang-Chun CHENG, William Weilun HONG, Liang-Guang CHEN, Kei-Wei CHEN
-
Patent number: 11675953Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.Type: GrantFiled: July 26, 2022Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin-Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
-
Patent number: 11637021Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: GrantFiled: May 18, 2021Date of Patent: April 25, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Sheng Lin, Chi-Jen Liu, Chi-Hsiang Shen, Te-Ming Kung, Chun-Wei Hsu, Chia-Wei Ho, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
-
Publication number: 20220382947Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.Type: ApplicationFiled: July 26, 2022Publication date: December 1, 2022Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin-Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
-
Patent number: 11443095Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.Type: GrantFiled: July 10, 2020Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
-
Publication number: 20220012400Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
-
Publication number: 20210371774Abstract: A cleaning composition for cleaning a surface of a substrate comprising silicon germanium after a chemical mechanical polishing process is provided. The cleaning composition includes an oligomeric or polymeric polyamine, at least one wetting agent, a pH adjusting agent, and a solvent.Type: ApplicationFiled: March 3, 2021Publication date: December 2, 2021Inventors: Ji CUI, William Weilun HONG, Gin-Chen HUANG, Shich-Chang SUEN, Kei-Wei CHEN
-
Patent number: 11189497Abstract: A method includes forming a film over a substrate; increasing a surface roughness of the film; and planarizing the film using a first chemical mechanical planarization (CMP) process after increasing the surface roughness.Type: GrantFiled: May 17, 2019Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chin Nien, Gang Huang, William Weilun Hong
-
Publication number: 20210343538Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
-
Patent number: 11133247Abstract: A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.Type: GrantFiled: July 29, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Wei Ho, Chun-Wei Hsu, Chi-Hsiang Shen, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
-
Publication number: 20210272818Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventors: Yi-Sheng LIN, Chi-Jen LIU, Chi-Hsiang SHEN, Te-Ming KUNG, Chun-Wei HSU, Chia-Wei HO, Yang-Chun CHENG, William Weilun HONG, Liang-Guang CHEN, Kei-Wei CHEN
-
Patent number: 11094555Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.Type: GrantFiled: May 19, 2020Date of Patent: August 17, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Yang-Chun Cheng
-
Publication number: 20210225657Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: April 1, 2021Publication date: July 22, 2021Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
-
Patent number: 11069533Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: GrantFiled: July 18, 2019Date of Patent: July 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
-
Patent number: 11037799Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.Type: GrantFiled: May 1, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng