Patents by Inventor Wein-Town Sun

Wein-Town Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180197875
    Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having a first OD region and a second OD region for forming an erase gate (EG) region. The second OD region is spaced apart from the first OD region and is separated from the first OD region by a trench isolation region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is also disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A first floating gate extension continuously extends from the floating gate to the second OD region. The first floating gate extension comprises a P+ doped segment and an N+ doped segment with a P+/N+ interface therebetween.
    Type: Application
    Filed: November 29, 2017
    Publication date: July 12, 2018
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Publication number: 20180197613
    Abstract: A method for operating a NVM cell is disclosed. The NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor on an N well. The floating gate transistor includes a floating gate and a floating gate extension capacitively coupled to an erase gate region. The method includes erasing the NVM cell by applying an N well voltage VNW to the N well, wherein VNW>0V; applying a source line voltage VSL to a source doping region of the select transistor, wherein VSL=0V; applying a word line voltage VWL to a select gate of the select transistor, wherein VWL=0V; applying a bit line voltage VBL to a drain doping region of the floating gate transistor, wherein VBL=0V; and applying an erase line voltage VEL to the erase gate region, wherein VEL=VEE .
    Type: Application
    Filed: December 7, 2017
    Publication date: July 12, 2018
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 9953685
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: April 24, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Jui-Ming Kuo, Chun-Yuan Lo, Chia-Jung Hsu, Wein-Town Sun
  • Publication number: 20180019252
    Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.
    Type: Application
    Filed: July 13, 2017
    Publication date: January 18, 2018
    Inventors: Chun-Hsiao Li, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 9812212
    Abstract: A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 7, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 9805806
    Abstract: A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.
    Type: Grant
    Filed: September 25, 2016
    Date of Patent: October 31, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun
  • Publication number: 20170207230
    Abstract: A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor layer, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor disposed on the first OD region. The PMOS floating gate transistor is serially connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension is continuously extended from the floating gate to the second OD region and is capacitively coupled to the second OD region.
    Type: Application
    Filed: December 20, 2016
    Publication date: July 20, 2017
    Inventors: Wein-Town Sun, Wei-Ren Chen, Ying-Je Chen
  • Publication number: 20170206975
    Abstract: A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 20, 2017
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun
  • Publication number: 20170207228
    Abstract: A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. The second floating-gate transistor includes a second floating gate with an extended portion extending on a second portion of the n-type erase region.
    Type: Application
    Filed: August 31, 2016
    Publication date: July 20, 2017
    Applicant: eMemory Technology Inc.
    Inventors: Ying-Je Chen, Wei-Ren Chen, Wein-Town Sun
  • Publication number: 20170110195
    Abstract: A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.
    Type: Application
    Filed: September 25, 2016
    Publication date: April 20, 2017
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 9484094
    Abstract: A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive random-access memory has a specified state. Then, an operation period begins. During a first sub-period of the operation period, a first control signal with a first polarity is provided. During a second sub-period of the operation period, a second control signal with a second polarity is provided. During a third sub-period of the operation period, a third control signal with the first polarity is provided. During a fourth sub-period of the operation period, a read signal is provided, so that the resistive random-access memory generates a read current. According to the read current, a controlling circuit verifies whether the resistive random-access memory is in the specified state.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 1, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Jung Hsu, Wein-Town Sun, Chun-Yuan Lo
  • Publication number: 20160211020
    Abstract: A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive random-access memory has a specified state. Then, an operation period begins. During a first sub-period of the operation period, a first control signal with a first polarity is provided. During a second sub-period of the operation period, a second control signal with a second polarity is provided. During a third sub-period of the operation period, a third control signal with the first polarity is provided. During a fourth sub-period of the operation period, a read signal is provided, so that the resistive random-access memory generates a read current. According to the read current, a controlling circuit verifies whether the resistive random-access memory is in the specified state.
    Type: Application
    Filed: October 1, 2015
    Publication date: July 21, 2016
    Inventors: Chia-Jung Hsu, Wein-Town Sun, Chun-Yuan Lo
  • Publication number: 20160148686
    Abstract: A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell is connected with the first word line. A first control terminal of the first memory cell is connected with a first source line of the first source line pair. A second control terminal of the first memory cell is connected with a second source line of the first source line pair. A third control terminal of the first memory cell is connected with the first bit line.
    Type: Application
    Filed: October 7, 2015
    Publication date: May 26, 2016
    Inventors: Chia-Jung Hsu, Wein-Town Sun, Ching-Sung Yang, Chi-Yi Shao, Chun-Yuan Lo, Yu-Hsiung Tsai, Ching-Yuan Lin
  • Publication number: 20150287738
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.
    Type: Application
    Filed: September 5, 2014
    Publication date: October 8, 2015
    Inventors: Jui-Ming Kuo, Chun-Yuan Lo, Chia-Jung Hsu, Wein-Town Sun
  • Publication number: 20150140766
    Abstract: A structure of a memory cell includes a substrate, a well, three source/drain doped regions, two bottom dielectric layers, two charge trapping layers, a blocking layer and two gates to form a storage transistor and a select transistor of the memory cell. A bottom dielectric layer and a charge trapping layer may be used to provide the dielectric of the gate of the select transistor with enough thickness but without any additional fabrication process.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 21, 2015
    Inventors: Wein-Town Sun, Cheng-Yen Shen
  • Publication number: 20150091077
    Abstract: A structure of a memory cell includes a substrate, a well, two source/drain doped regions, a stacked layer and a metal gate. The stacked layer includes a tunneling layer, and a charge trapping layer. A method of fabricating the memory cell may vary with the change in sequence of performing steps. The difference in sequence of fabrication may yield different characteristic variations for the formed components of the memory cell.
    Type: Application
    Filed: June 30, 2014
    Publication date: April 2, 2015
    Inventors: Wein-Town Sun, Cheng-Yen Shen
  • Publication number: 20150091080
    Abstract: A structure of a memory cell includes a substrate, a well, three source/drain doped regions, two bottom dielectric layers, two charge trapping layers, a blocking layer and two gates to form a storage transistor and a select transistor of the memory cell. A bottom dielectric layer and a charge trapping layer may be used to provide the dielectric of the gate of the select transistor with enough thickness but without any additional fabrication process.
    Type: Application
    Filed: July 8, 2014
    Publication date: April 2, 2015
    Inventors: Wein-Town Sun, Cheng-Yen Shen
  • Patent number: 8982634
    Abstract: The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 17, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Yuan-Tai Lin, Ching-Yuan Lin, Chao-Wei Kuo, Shang-Wei Fang, Wein-Town Sun
  • Patent number: 8837219
    Abstract: Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 16, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Kai-Yuan Hsiao, Wen-Yuan Lee, Yun-Jen Ting, Cheng-Jye Liu, Wein-Town Sun
  • Patent number: 8822319
    Abstract: A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 2, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Cheng-Yen Shen, Wein-Town Sun