Patents by Inventor Wen Hsiung Chang

Wen Hsiung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9370823
    Abstract: A metallic housing of an electronic device, includes a metallic outer frame and an inner structural member. The metallic outer frame comprises a plurality of latching portions protruding, and a plurality of latching grooves. The inner structural member is made from metal-alloy and embedded in the outer frame by die-casting. The inner structural member comprises a peripheral sidewall, a plurality of engaging portions, and a plurality of matching portions. The plurality of engaging portions and the plurality of matching portions protrude from the peripheral sidewall outwardly. Each latching portion comprises at least two parallel latching ribs, and forms a receiving groove between two adjacent latching ribs. The plurality of engaging portions is respectively embedded in the plurality of receiving grooves, and the plurality of matching portions is respectively embedded in the plurality of latching grooves. The present disclosure further provides a manufacturing method for the metallic housing.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: June 21, 2016
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Cai-Hua Wang, Yue-Jian Li, Chen-Shen Lin, Wen-Hsiung Chang, Chun-Jung Chang
  • Patent number: 9358606
    Abstract: A metallic housing of an electronic device includes a metallic outer case and an inner structural member embedded in the inner side of the outer case by die-casting. The outer case includes a bottom plate and a peripheral sidewall. The bottom plate is equipped with a number of latching hooks. The latching hooks are spaced from each other. The peripheral sidewall defines a receiving groove at an inner side along the peripheral sidewall. The inner structural member is made of metal alloy, and includes a base plate and a frame sidewall surrounding a periphery of the base plate, a protruding flange protruding from the frame sidewall, and a plurality of combining grooves on the base plate. The protruding flange is received in the receiving grooves, and the number of latching hooks is respectively received in the number of combining grooves.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: June 7, 2016
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Cai-Hua Wang, Yue-Jian Li, Chen-Shen Lin, Wen-Hsiung Chang, Chun-Jung Chang
  • Patent number: 9281332
    Abstract: In a package process of backside illumination image sensor, a wafer including a plurality of pads is provided. A first carrier is processed to form a plurality of blind vias therein. The first carrier is adhered to the wafer so that the blind vias face to the pads correspondingly. A spacing layer is formed and a plurality of sensing components are disposed. A second carrier is adhered on the spacing layer. Subsequently, a carrier thinning process is performed so that the blind vias become the through holes. An insulating layer is formed on the first carrier. An electrically conductive layer is formed on the insulating layer and filled in the though holes to electrically connect to the pads. The package process can achieve the exact alignment of the through holes and the pads, thereby increasing the package efficiency and improving the package quality.
    Type: Grant
    Filed: November 3, 2012
    Date of Patent: March 8, 2016
    Assignee: XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
    Inventor: Wen-Hsiung Chang
  • Publication number: 20150306661
    Abstract: A metallic article can include a cast metallic body and at least one metallic element. The cast metallic body defines at least one first space. The least one metallic element is received in the cast metallic body and seamless with the cast metallic body. The at least one metallic element is exposed from the at least one first space. A heat conductivity of the cast metallic body is lower than that of the at least one metallic element. The present disclosure further provides a method for manufacturing metallic article.
    Type: Application
    Filed: April 21, 2015
    Publication date: October 29, 2015
    Inventors: JUN-JUN YANG, CAI-HUA WANG, YUE-JIAN LI, CHEN-SHEN LIN, WEN-HSIUNG CHANG, CHUN-JUNG CHANG
  • Patent number: 9070672
    Abstract: Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: June 30, 2015
    Assignee: INEFFABLE CELLULAR LIMITED LIABILITY COMPANY
    Inventor: Wen-Hsiung Chang
  • Patent number: 8946085
    Abstract: A semiconductor process includes the following steps. Firstly, a conductive substrate is provided. Then, at least one insulating pattern is formed on the conductive substrate. Thereafter at least one metal pattern is formed on the insulating pattern. After that, a passivation layer is formed on the conductive substrate to cover the metal pattern by an electroplating process.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: February 3, 2015
    Assignee: Ineffable Cellular Limited Liability Company
    Inventor: Wen-Hsiung Chang
  • Publication number: 20150021064
    Abstract: A metallic housing of an electronic device, includes a metallic outer frame and an inner structural member. The metallic outer frame comprises a plurality of latching portions protruding, and a plurality of latching grooves. The inner structural member is made from metal-alloy and embedded in the outer frame by die-casting. The inner structural member comprises a peripheral sidewall, a plurality of engaging portions, and a plurality of matching portions. The plurality of engaging portions and the plurality of matching portions protrude from the peripheral sidewall outwardly. Each latching portion comprises at least two parallel latching ribs, and forms a receiving groove between two adjacent latching ribs. The plurality of engaging portions is respectively embedded in the plurality of receiving grooves, and the plurality of matching portions is respectively embedded in the plurality of latching grooves. The present disclosure further provides a manufacturing method for the metallic housing.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 22, 2015
    Applicants: FOXCONN TECHNOLOGY CO., LTD., FU ZHUN PRECISION INDUSTRY (SHEN ZHEN) CO., LTD.
    Inventors: CAI-HUA WANG, YUE-JIAN LI, CHEN-SHEN LIN, WEN-HSIUNG CHANG, CHUN-JUNG CHANG
  • Publication number: 20150021065
    Abstract: A metallic housing of an electronic device includes a metallic outer case and an inner structural member embedded in the inner side of the outer case by die-casting. The outer case includes a bottom plate and a peripheral sidewall. The bottom plate is equipped with a number of latching hooks. The latching hooks are spaced from each other. The peripheral sidewall defines a receiving groove at an inner side along the peripheral sidewall. The inner structural member is made of metal alloy, and includes a base plate and a frame sidewall surrounding a periphery of the base plate, a protruding flange protruding from the frame sidewall, and a plurality of combining grooves on the base plate. The protruding flange is received in the receiving grooves, and the number of latching hooks is respectively received in the number of combining grooves.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 22, 2015
    Applicants: FOXCONN TECHNOLOGY CO., LTD., FU ZHUN PRECISION INDUSTRY (SHEN ZHEN) CO., LTD.
    Inventors: CAI-HUA WANG, YUE-JIAN LI, CHEN-SHEN LIN, WEN-HSIUNG CHANG, CHUN-JUNG CHANG
  • Patent number: 8747532
    Abstract: A filter device for filtering dust from air includes a housing, a dust collecting module, a spraying module, and an exhaust. The housing defines an air inlet near a bottom of the housing and an air outlet near a top of the housing. The dust collecting module is installed in the housing between the air inlet and the air outlet. The spraying module is placed in the housing between the dust collecting module and the air outlet. The exhaust is connected to the housing for generating air pressure difference between near the air outlet and near the air inlet, thereby drawing and introducing air containing dust from the bottom of the housing toward the top of the housing via the air inlet.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Foxconn Technology Co., Ltd.
    Inventors: Chun-Jung Chang, Wen-Hsiung Chang, Ping-Neng Chang, Run-Cheng Lin
  • Patent number: 8685860
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 1, 2014
    Assignee: Ineffable Cellular Limited Liability Company
    Inventor: Wen-Hsiung Chang
  • Patent number: 8623689
    Abstract: In a package process of backside illumination image sensor, a wafer including a plurality of pads is provided. A first carrier is processed to form a plurality of blind vias therein. The first carrier is adhered to the wafer so that the blind vias face to the pads correspondingly. A spacing layer is formed and a plurality of sensing components are disposed. A second carrier is adhered on the spacing layer. Subsequently, a carrier thinning process is performed so that the blind vias become the through holes. An insulating layer is formed on the first carrier. An electrically conductive layer is formed on the insulating layer and filled in the though holes to electrically connect to the pads. The package process can achieve the exact alignment of the through holes and the pads, thereby increasing the package efficiency and improving the package quality.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: January 7, 2014
    Assignee: Ineffable Cellular Limited Liability Company
    Inventor: Wen-Hsiung Chang
  • Patent number: 8563405
    Abstract: A method for manufacturing semiconductor device includes the following steps. First, a carrier substrate and a plurality of pieced segments of wafer are provided. Each of the pieced segments of wafer has an active surface and a back surface on opposite sides thereof. Further, there is at least a bonding pad disposed on the active surface. Next, an adhering layer is formed between the carrier substrate and the active surfaces of the pieced segments of wafer, so as to make the pieced segments of wafer adhere to the carrier substrate. Next, a through silicon via is formed in each of the pieced segments of wafer to electrically connect to the bonding pad correspondingly. Then, the pieced segments of wafer are separated from the carrier substrate.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 22, 2013
    Assignee: Ineffable Cellular Limited Liability Company
    Inventor: Wen-Hsiung Chang
  • Publication number: 20130256842
    Abstract: Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.
    Type: Application
    Filed: June 3, 2013
    Publication date: October 3, 2013
    Inventor: Wen-Hsiung Chang
  • Patent number: 8460971
    Abstract: Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: June 11, 2013
    Assignee: Ineffable Cellular Limited Liability Company
    Inventor: Wen-Hsiung Chang
  • Publication number: 20130032032
    Abstract: A filter device for filtering dust from air includes a housing, a dust collecting module, a spraying module, and an exhaust. The housing defines an air inlet near a bottom of the housing and an air outlet near a top of the housing. The dust collecting module is installed in the housing between the air inlet and the air outlet. The spraying module is placed in the housing between the dust collecting module and the air outlet. The exhaust is connected to the housing for generating air pressure difference between near the air outlet and near the air inlet, thereby drawing and introducing air containing dust from the bottom of the housing toward the top of the housing via the air inlet.
    Type: Application
    Filed: December 5, 2011
    Publication date: February 7, 2013
    Applicant: FOXCONN TECHNOLOGY CO., LTD.
    Inventors: CHUN-CHUNG CHANG, WEN-HSIUNG CHANG, PING-NENG CHANG, RUN-CHENG LIN
  • Patent number: 8351138
    Abstract: A lens displacement device includes a flexible piece, a fixed element and a mobile element. The flexible piece has a support, a flexible part and an oscillation absorber. The flexible part connects to the support and at least one gap exists between the flexible part and the support. The oscillation absorber is installed in the gap between the flexible part and the support. Moreover, the fixed element couples to the support of the flexible piece, and the mobile element couples to the flexible part of the flexible piece. Furthermore, the flexible part of the flexible piece is deformed in shape for providing a restoration force with the mobile element. A manufacturing process of the flexible piece is also disclosed.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: January 8, 2013
    Assignee: Wah Hong Industrial Corp.
    Inventors: Li-Te Kuo, Chien-Liang Chen, Mei-Ling Lai, Wen-Hsiung Chang
  • Patent number: 8293640
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 23, 2012
    Assignee: Victory Gain Group Corporation
    Inventor: Wen-Hsiung Chang
  • Patent number: 8258007
    Abstract: A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: September 4, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Hui-Shan Chang, Wen-Hsiung Chang
  • Publication number: 20120205800
    Abstract: A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.
    Type: Application
    Filed: April 17, 2012
    Publication date: August 16, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Hui-Shan Chang, Wen-Hsiung Chang
  • Publication number: 20120049332
    Abstract: A semiconductor package and method for making the same are provided, wherein a lower chip having a plurality of conductive structures is bonded to an upper surface of a package substrate and a plurality of matrix walls are formed on the upper surface for surrounding the lower chip, such that an overcoat layer covering the matrix walls and the lower chip can be approximately removed after performing a grinding process to the lower chip to expose a plurality of conductive vias of the lower chip. The cleaning step for removing the residue of overcoat layer can be omitted, and the processing yield and the processing efficiency can be improved. The semiconductor package and the method is particularly suitable for stacking a large dimensional upper chip on a relatively small dimensional lower chip.
    Type: Application
    Filed: July 12, 2011
    Publication date: March 1, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jen-Chuan Chen, Hui-Shan Chang, Wen-Hsiung Chang, Wei-Nung Chang