Abstract: Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory address and the modified data in an associative memory coupled to a data cache and an instruction cache. In addition, the modified data is stored in a second level cache without invalidating the memory location associated with the instruction cache.

Abstract: Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory address and the modified data in an associative memory coupled to a data cache and an instruction cache. In addition, the modified data is stored in a second level cache without invalidating the memory location associated with the instruction cache.

Abstract: An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.

Abstract: A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions.

Abstract: A subset of a workload, which includes a total set of dynamic instructions, is identified to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at least one microprocessor and at least one cache. The real-time execution of the workload is monitored to obtain information about how the processor unit hardware executes the workload when the workload is executed using the particular dataset to form actual performance information. Multiple different subsets of the workload are generated. The execution of each one of the subsets by the processor unit hardware is compared with the actual performance information. A result of the comparison is used to select one of the plurality of different subsets that most closely represents the execution of the entire workload using the particular dataset to use as a trace.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a set of instructions are a set of instrumentation instructions in response to identifying the set of instructions in instructions for execution. A further determination is made as to whether a processor executing the instructions is in an instrumentation mode if the set of instructions are instrumentation instructions. The processor executes the set of instrumentation instructions only if the processor is in the instrumentation mode.

Abstract: A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions.

Abstract: Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.

Abstract: A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a processor executing a plurality of instructions is in an instrumentation mode. The processor has a normal set of resources and an alternate set of resources in which the alternate set of resources is associated with the instrumentation mode. When a determination is made that the processor is in the instrumentation mode, the processor executes instrumentation instructions in the plurality of instructions using the alternate set of resources and executes all other instructions in the plurality of instructions using the normal set of resources.

Abstract: A computer implemented method, apparatus, and computer usable medium for gathering performance related data in a multiprocessing environment. Instrumentation code is executed on a processor that minimizes the distortion to the processor resources used to execute the program to be profiled. Data is written by the instrumentation code to a shared memory in response to an event occurring during execution of the program. The data is generated during execution of the program on the processor and the instrumentation code uses shared memory to convey the data to a profiling application running on a set of profiling processors. The data is collected by the set of profiling processors in the shared memory written by the instrumentation code.

Abstract: A computer implemented method, apparatus and computer usable program code for marking instructions for instrumentation. A plurality of instructions is presented in a graphical user interface. A user input selecting a set of instructions in the plurality of instructions for instrumentation is received through the graphical user interface. A set of instructions is marked as a set of instrumentation instructions in response to receiving the user input. The set of instructions are executed by a processor if the processor is in an instrumentation mode, and the instrumentation instructions are unexecuted if an absence of the processor being in the instrumentation mode is present.

Abstract: A computer implemented method, apparatus and computer program product for processing instructions. A determination is made as to whether an instruction is a start instrumentation instruction in response to identifying the instruction for execution while executing the instructions using a normal set of processor resources in a processor. Subsequent instructions are executed using an alternate set of processor resources until an end instrumentation instruction is encountered.

Abstract: A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method.

Abstract: A method, apparatus, and computer-usable program code in a computer system for identifying a subset of a workload, which includes a total set of dynamic instructions, to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at least one microprocessor and at least one cache. The real-time execution of the workload is monitored to obtain information about how the processor unit hardware executes the workload when the workload is executed using the particular dataset to form actual performance information. Multiple different subsets of the workload are generated. The execution of each one of the subsets by the processor unit hardware is compared with the actual performance information. A result of the comparison is used to select one of the plurality of different subsets that roost closely represents the execution of the entire workload using the particular dataset to use as a trace.

Abstract: Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.

Abstract: An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.

Abstract: A system for prioritizing resource requests. One or more resource requests are received. The one or more resource requests are prioritized in a queue according to a priority attribute that is associated with each of the one or more resource requests. A resource request with a highest priority in the queue is selected and processed. Then, a response to the resource request with the highest priority is sent.

Abstract: A system for making a determination to send a synchronous or asynchronous resource request. In response to sending a request to receive response time data for resource requests, the response time data for resource requests is received and stored. A request from a requester is received for response time data for a particular type of resource request. The response time data for the resource requests is searched for the particular type of resource request. In response to finding the response time data for the particular type of resource request within the response time data for the resource requests, the response time data for the particular type of resource request is sent to the requester. The requester either sends a synchronous or asynchronous resource request based on the response time data for the particular type of resource request.

Abstract: The present invention provides for a plurality of partitioned ways of an associative cache. A pseudo-least recently used binary tree is provided, as is a way partition binary tree, and signals are derived from the way partition binary tree as a function of a mapped partition. Signals from the way partition binary tree and the pseudo-least recently used binary tree are combined. A cache line replacement signal is employable to select one way of a partition as a function of the pseudo-least recently used binary tree and the signals derived from the way partition binary tree.